Re: errata/282: signing

From: Alec Stanculescu (alec@fintronic.com)
Date: Tue May 04 2004 - 11:10:00 PDT

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    The following reply was made to PR errata/282; it has been noted by GNATS.

    From: Alec Stanculescu <alec@fintronic.com>
    To: stefen@boyd.com
    Cc: etf-bugs@boyd.com
    Subject: Re: errata/282: signing
    Date: Tue, 4 May 2004 11:26:27 -0700

     Stefen,
     
     I agree with everything you said, with the possible exception that you
     appear to be of the opinion that the writing of the LRM was
     successful in making "sign rules follow vector width rules". This is
     not the case because sign rules change the sign of operands (from what
     they were specified by the user!) whereas vector width rules do not
     affect what the user wrote, they do not change the width of any
     operand. They just describe what happens to the result.
     
     In my opinion it is better to tell the user that his/her code will have to be
     changed and not change it for them. Currently, there are some rules
     regarding how to fix what the user wrote in terms of signed/unsinged
     and there is disagreement regarding how to interpret these rules. I am
     saying that there is no need for such rules in the first place. Give
     the user the chance to write correct and portable code, without taking
     from the user any modeling power.
     
     Regards,
     
     Alec
     
    > Alec,
    >
    > This has been rather heated discussion and I don't intend to stoke
    > the fire...
    > As a user, I was there during the discussions when we added signed
    > arithmetic. Perhaps I don't represent all of the users, but for a
    > portion of them I may represent, I understood the way signed
    > arithmetic was defined and it made sense to me. I'm not sure I'm
    > excited about making expressions that mix signs illegal. Having it
    > behave the same way as vector expansion made sense then and still
    > does now. As a user, I like the consistency of the two rules. They
    > may be weird, but since they're the same, once I've understood the
    > one - I understand both. I'm not opposed to rethinking the sign
    > rules but I'd like them to match something else in Verilog.
    > And, no, making it illegal rubs me the wrong way - it's not very
    > Verilog, so that wouldn't get me excited either.
    >
    > I'm not trying to point fingers here, I'm just saying that regardless
    > of how well it was documented, our intent was for sign rules to
    > follow the vector width rules. And strange as it may seem - I liked
    > it that way. That's why I approved it in the standard... I'd just like
    > to see it cleaned up to document what we intended when we were
    > refining the proposal.
    >
    > Stefen
    >
    > At 05:40 PM 5/3/2004 -0700, Alec Stanculescu wrote:
    > > So, what do you say to the proposal to make illegal any complex expression
    > > that uses both signed and unsigned. This could simplify the LRM
    > > enormously and users would see only benefits from this, since they
    > > would not loose any modeling capabilities they currently have, and
    > > models would be portable across tools.
    >
     

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