Re: errata/282: signing

From: Alec Stanculescu (alec@fintronic.com)
Date: Tue May 04 2004 - 15:30:00 PDT

  • Next message: Steven Sharp: "implementation notes on `line directive"

    The following reply was made to PR errata/282; it has been noted by GNATS.

    From: Alec Stanculescu <alec@fintronic.com>
    To: Shalom.Bresticker@freescale.com
    Cc: etf-bugs@boyd.com
    Subject: Re: errata/282: signing
    Date: Tue, 4 May 2004 15:43:02 -0700

     Shalom,
     
     You are right.
     
     And this is exactly the same as in C/C++ as is exemplified by the
     following C code:
     #include <stdio.h>
     
     int main()
     {
        short b;
        unsigned a;
        b = 12;
        a = ~b;
        printf("a=%x\n", a);
     }
     
     producing:
     
     a=fffffff3
     
     You convinced me that size and sign are two very
     different things and that the mirage of trying to treat them in the
     same way attracted many people, and would have attracted me as well if
     I would have been involved in that decision process.
     
     The corresponding C code for the issue 282 under discussion is:
     
     #include <stdio.h>
     
     int main()
     {
        short s;
        short int a, b;
        unsigned result, d;
        d = 3;
        a = -2;
        b = 1;
        result = d + a * b;
        printf("result=%d\n", result);
     }
     
     which produces result = 1
     
     Following the semantics of C/C++ whenever possible was always a big
     plus for Verilog and I think that we should make efforts to keep it
     this way for obvious reasons.
     
     Therefore, the following code:
     
     `timescale 1ns/1ns
     module test;
     
       reg signed [15:0] a,b;
       reg [31:0] result, d;
       integer v;
       initial
         begin
           v = 3;
           d = v;
           v = -2;
           a = v;
           v = 1;
           b = v;
           result = d + a * b;
           $display("a = %b,\n b = %b,\n d = %b,\n result = %b\n",a,b,d,result);
           $finish;
         end // initial begin
     
     endmodule // test
     
     should produce:
      a = 1111111111111110,
      b = 0000000000000001,
      d = 00000000000000000000000000000011,
      result = 00000000000000000000000000000001
     
     Also, please note that
     
     `timescale 1ns/1ns
     module test;
     
       reg [7:0] a;
       reg [3:0] b;
     
       initial
         begin
           b = 4'b1100;
           a = {4'b0000, ~b};
           $display("a = %b, b = %b",a,b);
           $finish;
         end // initial begin
     
     endmodule // test
     should produce the result:
     
     a = 00000011, b = 1100
     
     because b should not be sign-extended in this case, due to the fact
     that the LHS matches the RHS in size. Therefore, the LRM does not
     impose blindly the extension of all operands to the largest size as it is not
     imposing to blindly coerce all operands to unsigned if one operand is
     unsigned.
     
     Alec Stanculescu
     
    > Shalom Bresticker wrote:
    > Alec,
    >
    > > I agree with everything you said, with the possible exception that you
    > > appear to be of the opinion that the writing of the LRM was
    > > successful in making "sign rules follow vector width rules". This is
    > > not the case because sign rules change the sign of operands (from what
    > > they were specified by the user!) whereas vector width rules do not
    > > affect what the user wrote, they do not change the width of any
    > > operand. They just describe what happens to the result.
    >
    > This is not so.
    > Consider this case:
    >
    > a is 8 bits, b is 4 bits, b = 4'b1100
    >
    > If I write
    >
    > a = ~b;
    >
    > then b is first widened to 8 bits, giving me 8'b00001100.
    > When I complement it, I get a = 8'b11110011.
    >
    > Whereas if I first complemented b, then widened the result,
    > I would get 8'b00000011.
    >
    > Shalom
    >
     

    This archive was generated by hypermail 2.1.4 : Tue May 04 2004 - 15:30:08 PDT and
    sponsored by Boyd Technology, Inc.