From: Steven Sharp (sharp@cadence.com)
Date: Thu May 06 2004 - 13:50:00 PDT
The following reply was made to PR enhancement/350; it has been noted by GNATS.
From: Steven Sharp <sharp@cadence.com>
To: etf-bugs@boyd.com
Cc:
Subject: enhancement/350: BNF issues
Date: Thu, 6 May 2004 17:09:32 -0400 (EDT)
I was looking at the BNF to see what would need to be changed to restrict
configs to library mapping files. I discovered that the BNF already doesn't
seem to allow configs in Verilog source. And this single grammar seems to
be trying to define two different languages at the same time.
It is not clear in the BNF what the starting nonterminal for the language is.
Normally this would be the first nonterminal defined. In this case, that is
library_text. But if you follow that down, you find that it defines the
language of library mapping files. This is not Verilog. Library declarations
are not allowed in Verilog source, and you can't get to Verilog source
starting from library_text.
The starting nonterminal for Verilog appears to be source_text, which makes
sense and matches the BNF in the 1995 standard. This needs to be the first
nonterminal in the grammar, or the Annex needs to state that it is the
starting nonterminal for the Verilog language.
It looks to me like the simplest solution would be to state at the top of
the Annex that the Verilog language is derived from the starting nonterminal
source_text, and that library mapping file syntax is derived from the
starting nonterminal library_text.
Should I file this as a separate erratum, or fold it into the changes for
this enhancement request?
Note that if you follow the BNF, you can get to a config_declaration from
library_text, but you cannot get to it from source_text. So the BNF already
says that configs are not allowed in Verilog source, only in library mapping
files. No BNF changes are specifically required for this enhancement.
Steven Sharp
sharp@cadence.com
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