enhancement/350: PROPOSAL - Deprecate configs in Verilog source

From: Steven Sharp (sharp@cadence.com)
Date: Tue May 11 2004 - 12:10:00 PDT

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    The following reply was made to PR enhancement/350; it has been noted by GNATS.

    From: Steven Sharp <sharp@cadence.com>
    To: etf-bugs@boyd.com
    Cc:
    Subject: enhancement/350: PROPOSAL - Deprecate configs in Verilog source
    Date: Tue, 11 May 2004 15:24:22 -0400 (EDT)

     Proposal to allow configs only in the library mapping file. The changes for
     this are not extensive, since there is no text that states that configs can
     appear in Verilog source, and only a few sentences that imply it. The BNF
     never actually allowed it.
     
     I used <angle-brackets> to show keywords that should be bold.
     
     
     In 13.1 REPLACE
     
       As evidenced by the <config>-<endconfig> syntax, the config is a design
       element, similar to a module, which exists in the Verilog namespace.
       The config contains a set of rules which are applied when searching
       for a source description to bind to a particular instance of the design.
     
     WITH
     
       A config definition shall be enclosed between the keywords <config>
       and <endconfig>. The identifier following the keyword <config> shall
       be the name of the config. The config is a design element containing
       a set of rules which are applied when searching for a source description
       to bind to a particular instance in the design.
     
       A config shall not appear in a Verilog source description. It shall
       appear only in a library mapping file (see 13.2.1).
     
       Note - IEEE Std 1364-2001 did not state that configs could not appear
       in Verilog source descriptions, implying that they could.
     
     
     In 13.2.1 REPLACE
     
       The syntax for declaring a library in the library map file is shown
       in Syntax 13.2.
     
     WITH
     
       The syntax for declaring a library in the library map file is shown
       in Syntax 13.2.
     
       The library mapping file has a syntax which is distinct from the
       syntax of Verilog source files. It uses some keywords which are not
       considered keywords in Verilog HDL (<cell>, <config>, <design>,
       <endconfig>, <include>, <instance>, <liblist>, <library>, <use>).
       A library mapping file can still reference a cell name that matches a
       library mapping file keyword by using an escaped identifier (see 2.7.1).
     
     
     In 13.4.4 REPLACE
     
       In the single-pass use-models, the config can be specified by including
       its source description on the command line.
     
     WITH
     
       In the single-pass use-models, the config can be specified by including
       it in the library mapping file.
     
     
     In 13.4.4 REPLACE
     
       In this strategy, the config itself shall also be precompiled.
     
     WITH
     
       In this strategy, a specified config can be obtained from the library
       mapping file, or the tool can provide a mechanism for precompiling
       configs into a library like other cells.
     
     
     In Annex A, under "Formal syntax definition", REPLACE
     
       The formal syntax of Verilog HDL is described using Backus-Naur Form (BNF).
     
     WITH
     
       The formal syntax of Verilog HDL is described using Backus-Naur Form (BNF).
       The syntax of Verilog HDL is derived from the starting symbol source_text.
       The syntax of a library mapping file is derived from the starting symbol
       library_text.
     
     
     In Annex B, under "List of keywords", REPLACE
     
       An escaped identifier shall not be treated as a keyword.
     
     WITH
     
       An escaped identifier shall not be treated as a keyword.
     
       These are the keywords for Verilog HDL:
     
     
     From the keyword list, DELETE
     
       <cell>, <config>, <design>, <endconfig>, <incdir>, <include>,
       <instance>, <liblist>, <library>, <use>
     
     
     After the keyword list, ADD
     
       These are the keywords for a library mapping file:
     
       <cell>, <config>, <default>, <design>, <endconfig>, <include>,
       <instance>, <liblist>, <library>, <use>
     
     
     Note that <default> appears in the library mapping file keywords, but
     is not removed from the Verilog HDL keywords. It is a keyword in both.
     The keyword <incdir> is removed from the Verilog HDL keywords, but is
     not added to the library mapping file keywords. This is because the
     syntax does not appear to require reserving <incdir> because it always
     appears after a hyphen. However, it could still be added to the list
     of library mapping file keywords if desired.
     
     
     

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