RE: enhancement/350: PROPOSAL - Deprecate configs in Verilog sour ce

From: Brophy, Dennis (dennisb@model.com)
Date: Thu May 13 2004 - 08:10:00 PDT

  • Next message: Steven Sharp: "RE: enhancement/350: PROPOSAL - Deprecate configs in Verilog source"

    The following reply was made to PR enhancement/350; it has been noted by GNATS.

    From: "Brophy, Dennis" <dennisb@model.com>
    To: Jayaram Bhasker <JBhasker@esilicon.com>, etf-bugs@boyd.com
    Cc:
    Subject: RE: enhancement/350: PROPOSAL - Deprecate configs in Verilog sour
            ce
    Date: Thu, 13 May 2004 08:29:51 -0700

     All,
     
     I think it is a bad idea to regress behavior that is already supported in 2001. Configs should not be restricted to only appear in library map files since this restriction was not in place for the 2001 spec.
     
     Users have come to use configs in other places other than library map files and I am hard pressed to see how we can now rationalize it out of being used in other places moving forward.
     
     -Dennis
     
     -----Original Message-----
     From: owner-etf@boyd.com [mailto:owner-etf@boyd.com] On Behalf Of Jayaram Bhasker
     Sent: Wednesday, May 12, 2004 3:50 PM
     To: etf-bugs@boyd.com
     Subject: RE: enhancement/350: PROPOSAL - Deprecate configs in Verilog source
     
     The following reply was made to PR enhancement/350; it has been noted by GNATS.
     
     From: "Jayaram Bhasker" <JBhasker@eSilicon.com>
     To: "Shalom Bresticker" <Shalom.Bresticker@freescale.com>, <etf-bugs@boyd.com>
     Cc:
     Subject: RE: enhancement/350: PROPOSAL - Deprecate configs in Verilog source
     Date: Wed, 12 May 2004 09:14:51 -0400
     
      If configs are limited to occur in library map files, how would configs be referenced within configs? Is the idea not to allow a config to reference other configs?
      
      In the current config definition, a config can be in a file, the file is compiled into a library and the library.config can be referenced in another config.
      
      regards,
      - bhasker
      
      
      -----Original Message-----
      From: Shalom Bresticker [mailto:Shalom.Bresticker@freescale.com]
      Sent: Wednesday, May 12, 2004 5:50 AM
      To: etf-bugs@boyd.com
      Subject: Re: enhancement/350: PROPOSAL - Deprecate configs in Verilog source
      
      
      The following reply was made to PR enhancement/350; it has been noted by GNATS.
      
      From: Shalom Bresticker <Shalom.Bresticker@freescale.com>
      To: Steven Sharp <sharp@cadence.com>
      Cc: btf-bugs@boyd.com
      Subject: Re: enhancement/350: PROPOSAL - Deprecate configs in Verilog source
      Date: Wed, 12 May 2004 13:00:26 +0300
      
    > The keyword <incdir> is removed from the Verilog HDL keywords, but is
    > not added to the library mapping file keywords. This is because the
    > syntax does not appear to require reserving <incdir> because it always
    > appears after a hyphen. However, it could still be added to the list
    > of library mapping file keywords if desired.
       
       This is related to the question of whether white space is allowed between
       the hyphen and <incdir>. If not, what is the lexical token here?
       
       Shalom
      
     

    This archive was generated by hypermail 2.1.4 : Thu May 13 2004 - 08:10:29 PDT and
    sponsored by Boyd Technology, Inc.