From: Shalom.Bresticker@freescale.com
Date: Sat May 29 2004 - 22:10:00 PDT
The following reply was made to PR enhancement/547; it has been noted by GNATS.
From: Shalom.Bresticker@freescale.com
To: btf-bugs@boyd.com
Cc:
Subject: Re: enhancement/547: define size zero replication constant
Date: Sun, 30 May 2004 08:24:43 +0300 (IDT)
An independent development of the same enhancement:
---------- Forwarded message ----------
Date: 28 May 2004 23:03:05 GMT
From: Steve Meyer <sjmeyer@www.tdl.com>
Reply-To: sjmeyer@pragmatic-c.com
Newsgroups: comp.lang.verilog
Subject: Re: Repeat concatenation and Modelsim
GPL Cver allows 0 width concats because a user we were not matching XL.
The algorithm is that a 0 repeat count removes the element. It is then
an error if the entire concatenate disappers (i.e. becomes zero width).
Here is the bug report test:
============
module top;
reg [10:0] rf_addr_ext;
reg [10:0] rf_addr;
parameter AW = 5;
parameter DW = 5;
initial begin
rf_addr_ext = {{AW - DW{1'b0}}, rf_addr};
end
endmodule
============
On Tue, 25 May 2004 16:18:38 +0100, DW <dave_wooff@hotmail.com> wrote:
> Hello,
> Can anyone confirm that the Verilog language definition rules out a repeat
> concatenation of 0. i.e.
> {0{1'b1}} is NOT allowed.
>
> Modelsim Altera v5.7e seems to let this pass and produces invalid code.
> Quartus II version 3.0 seems to reject the use of this, although I have been
> informed that a later release (version 4.0 I believe) allows it (when it
> apparently should not).
>
> Although the example given is simplistic, I had used a combination of
> defparam'd parameters which produced the 0 repeat. I do not have a complete
> language reference (could be a good investment).
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