errata/586: signedness of case expression size extensions (9.5)

From: sharp@cadence.com
Date: Wed Jun 09 2004 - 15:28:59 PDT

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    >Number: 586
    >Notify-List:
    >Category: errata
    >Originator: sharp@cadence.com (Behavioral Task Force)
    >Environment:
    >Description:

    This issue was posted to comp.lang.verilog. Section 9.5
    on case statements says that "The length of all the case
    item expressions, as well as the case expression in the
    parentheses, shall be made equal to the length of the
    longest case expression and case item expression." It
    does not say anything about the signedness of these
    expressions, which would affect how they were extended.

    It is my opinion, as I stated in errata/344, that case
    expressions and case item expressions should be treated
    as operands of a really big compare "operator". This
    means that if any operand is unsigned, they should all
    be treated as unsigned. This is consistent with the rest
    of the language rules, where operands that affect each
    others size also affect each others signedness (with the
    one explicitly stated exception that the left-hand-side
    of an assignment does not affect the signedness of the
    right-hand-side).

    The posting stated that different simulators treated this
    differently. I have verified that the implementation in
    Verilog-XL, which was the basis for the original proposal,
    matches the interpretation I have suggested. Unfortunately,
    NC-Verilog does not, instead treating the signedness of
    each expression as self-determined. If this interpretation
    is adopted, we would need to fix the tool.

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