Re: errata/586: case signedness testcase

From: Shalom.Bresticker@freescale.com
Date: Tue Jun 29 2004 - 23:01:44 PDT

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    I think you should attach them.

    600 lines is not too long.

    Shalom

    On Tue, 29 Jun 2004, Steven Sharp wrote:

    > I have a copy of the Verilog testcase that was used by the person who
    > discovered the differences among simulators in this area. If any other
    > implementors would be interested in having the testcase, I can make it
    > available.
    >
    > There are actually two variations of the testcase. Each is around 300
    > lines, because they include if-then-else codings that mimic various
    > possible approaches to evaluating the case, for comparison. That might
    > be too long for directly attaching to this erratum.
    >
    > Steven Sharp
    > sharp@cadence.com
    > 

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Shalom Bresticker                         Shalom.Bresticker @freescale.com
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