Forward compatibility of Verilog generate regions

From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Thu Jul 29 2004 - 10:23:13 PDT

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    Is it correct that tools that fully support old-style Verilog generate
    regions are forward compatible with new-style Verilog generate regions?

    That is, if one always uses the generate/endgenerate brackets and conforms
    to the syntax restrictions of the new-style generate, will a tool that
    is fully compliant with old-style generate be able to parse it, and will
    the results be the same?

    If not, what are the differences?

    It would be good to document a subset of new-style generate that is
    guaranteed to work on tools that fully and perfectly implement the
    original 2001 standard.

    -- Brad

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