Re: errata/608: mintypmax_expression usage

From: Shalom.Bresticker@freescale.com
Date: Sat Jul 31 2004 - 13:00:00 PDT

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    The following reply was made to PR errata/608; it has been noted by GNATS.

    From: Shalom.Bresticker@freescale.com
    To: Brad Pierce <Brad.Pierce@synopsys.com>
    Cc: etf-bugs@boyd.com
    Subject: Re: errata/608: mintypmax_expression usage
    Date: Sat, 31 Jul 2004 23:01:27 +0300 (IDT)

     Synthesis tools may not implement such a switch, but there is nothing
     inherent in the mintypmax feature which makes it unusable in synthesis.
     
     The name "mintypmax" indicates its typical use,
     the reason the feature was created in Verilog,
     but once existing, it can be used for other purposes as well.
     
    > There's usually a simulator switch to control whether to pick up
    > min, typ or max, with typ as the default. A common use is explore
    > the potential impact of the library cell delay factors. (Mintypmax
    > expressions have no meaning in synthesis.)
     
     Shalom
     

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