From: Eric Mahurin (eric_mahurin@yahoo.com)
Date: Sat Jul 31 2004 - 14:00:00 PDT
The following reply was made to PR errata/608; it has been noted by GNATS.
From: Eric Mahurin <eric_mahurin@yahoo.com>
To: Shalom.Bresticker@freescale.com, etf-bugs@boyd.com
Cc:
Subject: Re: errata/608: mintypmax_expression usage
Date: Sat, 31 Jul 2004 14:00:18 -0700 (PDT)
One problem I see is if you wanted to make a simulator
that didn't default to min, typ, or max for delays,
but instead effectively simulated a range of delays.
For example:
a = 1'b0;
#1:2:3;
a = 1'b1;
You might want to treat this equivalent to:
a = 1'b0;
#1;
a = 1'bX;
#2; // time=3
a = 1'b1;
This way you would be simulating the entire delay
range at once. I don't think min:typ:max would make
any sense anywhere except delays if you wanted to do
such a thing.
Eric
--- Shalom.Bresticker@freescale.com wrote:
> Synthesis tools may not implement such a switch,
> but there is nothing
> inherent in the mintypmax feature which makes it
> unusable in synthesis.
>
> The name "mintypmax" indicates its typical use,
> the reason the feature was created in Verilog,
> but once existing, it can be used for other
> purposes as well.
>
> > There's usually a simulator switch to control
> whether to pick up
> > min, typ or max, with typ as the default. A
> common use is explore
> > the potential impact of the library cell delay
> factors. (Mintypmax
> > expressions have no meaning in synthesis.)
>
> Shalom
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