errata/619: what is the width of a range with z and x's in the bouns

From: fm@cadence.com
Date: Thu Aug 12 2004 - 12:20:31 PDT

  • Next message: Shalom.Bresticker@freescale.com: "Re: errata/619: what is the width of a range with z and x's in the bounds"

    >Number: 619
    >Notify-List:
    >Category: errata
    >Originator: Francoise Martinolle
    >Environment:
    >Description:

    The Verilog LRM does not specify what happens if an data declaration
    uses a range which left and or right bound has x or z bits.

    example:
    reg [7:1'bz] r;
    parameter [2'bxz: 8] p = 33;
    function [7:1'bx] set;
    wire [4:1'bz] w;

    Verilog xl accepts all of the above and apparently ignores the x or z bits.
    In the above the register has a width [7:0]

    I suppose that we should describe this behaviour in the LRM?

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