David Russinoff paper about 1364 Scheduling (cf. issue #57)

From: Shalom Bresticker (Shalom.Bresticker@freescale.com)
Date: Tue Aug 17 2004 - 01:08:44 PDT

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    A Note on the IEEE Verilog Simulation Cycle

                                       David M. Russinoff

                                           Abstract

    The IEEE Verilog Standard contains a number of ambiguities and inconsistencies
    with respect to the semantics of event scheduling, creating difficulties for the
    programmer in predicting the behavior of a compliant simulator. In this note, we
    bring some of these issues to light and attempt to resolve them by outlining an
    abstract formulation of the Verilog simulation cycle, aimed at clarifying the
    intent of the Verilog Standard Committee. We also observe that the degree of
    freedom allowed by the Standard in the interleaving of concurrent processes is
    impractical, and if fully exercised, would inevitably lead to race conditions
    and unpredicable results. Consequently, this aspect of the specification has
    been essentially ignored by tacit agreement between implementors and users. As a
    remedy, we propose to modify the specification of the simulation cycle by
    imposing a simple restriction on the nondeterministic selection of active
    events. The suggested restriction would allow the programmer to eliminate race
    conditions without inhibiting compiler optimization.

    You can see more about David at
    http://nitro.xyzdns.net/~russ/david/publications.html 

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Shalom Bresticker                        Shalom.Bresticker @freescale.com
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