Re: Verilog 2001 (1364-2001):issue::same_inputs as module declaration

From: Shalom Bresticker (Shalom.Bresticker@freescale.com)
Date: Thu Sep 09 2004 - 05:25:56 PDT

  • Next message: Stefen Boyd: "Fwd: Failed submission from Bineet SRIVASTAVA <bineet.srivastava@st.com>"

    You seem to have an old version of the LRM.

    If you look at 1364-2001 Version C, or 1364-2005 Draft 3, you will see that
    instead of "ored together", it says "tied together".

    Shalom

    Bineet SRIVASTAVA wrote:

    > hi all,
    >
    > As per LRM 1364-2001 of Verilog HDL
    >
    > in module declaration
    >
    > module same_input (a,a);
    > input a; // This is legal. The inputs are ored together.
    >
    > If u use the same kind of construct & simulate with VCS
    > it doesn't reflect the 'or'ing of inputs
    >
    > inputs output
    > 0 0 0
    > 1 1 1
    > 0 1 x
    > 1 x x
    > 0 x x
    > 1 0 x
    >
    > any comments.......
    >
    > regards
    > bineet 

    --
Shalom Bresticker                        Shalom.Bresticker @freescale.com
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