errata/641: Issue::IEEE P1364-2005/D2, 5/26/03: ambiguity in port declaration rule

From: Bineet SRIVASTAVA (bineet.srivastava@st.com)
Date: Tue Nov 30 2004 - 02:10:01 PST

  • Next message: Shalom.Bresticker@freescale.com: "Re: errata/641: ambiguity in port declaration rule"

    >Number: 641
    >Category: errata
    >Originator: Bineet SRIVASTAVA <bineet.srivastava@st.com>
    >Description:

    In section : 12.3.3 for port declarations

    "If a port declaration does not include a net or variable type, then the port can be again declared in a net or
    variable declaration. If the net or variable is declared as a vector, the range specification between the two
    declarations of a port shall be identical. Once a name is used in a port declaration it shall not be declared
    again in another port declaration or in a data type declaration."

    Example:
    module A(b);
    .
    output b;
    reg b; //now port b of type 'reg'
    .

    endmodule

    But nothing has been said for the vice versa case of :
    "If a port declaration does not include a net or variable type, then the port can be again declared in a net or
    variable declaration."

    module A(b);
    .
    reg b;
    output b;
    /* Clean semantic for above statements or Error!!! */

    .

    endmodule

    Leading to mismatches among tools..
    e.g.

    Synplify_pro - Error
    VCS - Pass
    Formality - Error

    Well I dint checked many!!

    guess..elaboration of the sentence is required.

    What do you think.

    Regards
    Bineet Srivastava
    ST Microlectronics Ltd.
    NOIDA, INDIA

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