errata/651: 14.2.4.2, Example 2: last => should be *>

From: Shalom Bresticker (Shalom.Bresticker@freescale.com)
Date: Tue Feb 15 2005 - 22:30:00 PST

  • Next message: Shalom.Bresticker@freescale.com: "errata/652: 14.2.4.3, Example 2: path conditions not unique?"

    >Number: 651
    >Category: errata
    >Originator: Shalom Bresticker <Shalom.Bresticker@freescale.com>
    >Description:

    In 14.2.4.2, Example 2:

    module ALU (o1, i1, i2, opcode);
    input [7:0] i1, i2;
    input [2:1] opcode;
    output [7:0] o1;

    //functional description omitted
    specify

    // add operation

    if (opcode == 2'b00) (i1,i2 *> o1) = (25.0, 25.0);

    // pass-through i1 operation

    if (opcode == 2'b01) (i1 => o1) = (5.6, 8.0);

    // pass-through i2 operation

    if (opcode == 2'b10) (i2 => o1) = (5.6, 8.0);

    // delays on opcode changes

    (opcode => o1) = (6.1, 6.5);
    endspecify
    endmodule

    In the last delay specification,

    (opcode => o1) = (6.1, 6.5);

    the => (parallel path) should be *> (full path).

    => requires that the same size vector should be on both sides, input and output.

    Verilog-XL indeed flags a syntax error.

    Besides, the intent really is that each bit of opcode affects all of o1, which
    is what *> does.

    Shalom 

    --
Shalom Bresticker                        Shalom.Bresticker @freescale.com
Design & Verification Methodology                    Tel: +972 9  9522268
Freescale Semiconductor Israel, Ltd.                 Fax: +972 9  9522890
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