Re: errata/651: 14.2.4.2, Example 2: last => should be *>

From: Shalom.Bresticker@freescale.com
Date: Thu Feb 17 2005 - 00:50:01 PST

  • Next message: Shalom.Bresticker@freescale.com: "14.2.4.3 grammar error"

    The following reply was made to PR errata/651; it has been noted by GNATS.

    From: Shalom.Bresticker@freescale.com
    To: etf-bugs@boyd.com
    Cc:
    Subject: Re: errata/651: 14.2.4.2, Example 2: last => should be *>
    Date: Thu, 17 Feb 2005 11:03:21 +0200 (IST)

     I found in the Verilog-XL LRM that it is indeed "*>".
     
     So I will treat this as a clear typo and fix it in the ballot draft.
     
     
    > In the last delay specification,
    >
    > (opcode => o1) = (6.1, 6.5);
    >
    > the => (parallel path) should be *> (full path).
     
     Shalom
     

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