14.2.4.3 grammar error

From: Shalom.Bresticker@freescale.com
Date: Thu Feb 17 2005 - 01:10:56 PST

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    In 14.2.4.3, it says,m

    "In this example, if the positive edge of clock occurs when reset and clear are low, and a module path extends from clock to out using a rise delay of 10 and a fall delay of 8."

    I deleted the word "and" before "a module path".

    Shalom 

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Shalom Bresticker                        Shalom.Bresticker @freescale.com
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