Re: errata/652: 14.2.4.3, Example 2: path conditions not unique?

From: Shalom.Bresticker@freescale.com
Date: Sat Feb 19 2005 - 12:20:00 PST

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    The following reply was made to PR errata/652; it has been noted by GNATS.

    From: Shalom.Bresticker@freescale.com
    To: etf-bugs@boyd.com
    Cc:
    Subject: Re: errata/652: 14.2.4.3, Example 2: path conditions not unique?
    Date: Sat, 19 Feb 2005 22:35:00 +0200 (IST)

     I looked at the Verilog-XL LRM. The examples there are slightly different
     but similar enough that I can speculate that originally these were two
     different examples of pairs of unique conditions, and they were mistakenly
     combined into a single example of 4 conditions.
     
    > 14.2.4.3 says that "Different delays can be made to the same edge-sensitive
    > path as long as ... the edge, condition, or both make each declaration
    > unique".
    >
    > Then follows Example 2:
    >
    > "The following example shows four edge-sensitive path declarations. Note
    > that each path has a unique edge or condition.
    >
    > specify
    > ( posedge clk => ( q[0] : data ) ) = (10, 5) ;
    > ( negedge clk => ( q[0] : data ) ) = (20, 12) ;
    >
    > if (reset)
    > ( posedge clk => ( q[0] : data ) ) = (15, 8) ;
    > if (!reset && cntrl)
    > ( posedge clk => ( q[0] : data ) ) = ( 6, 2) ;
    > endspecify"
    >
    > I don't see the uniqueness between the 1st and 3rd or 1st and 4th path
    > declarations.
    >
    > The 1st is unconditional on the same path as the 3rd and 4th with the
    > same edge, so it seems to overlap with both of them.
     
     Shalom
     

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