specify block edge-sensitive path description syntax question

From: Shalom Bresticker (Shalom.Bresticker@freescale.com)
Date: Wed Feb 23 2005 - 07:22:34 PST

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    Question:

    I received a behavioral model of a memory from our memory group which includes
    specify blocks.

    The interesting lines look like this:

       specify
         specparam trstq = 0.000;
         (negedge reset_b +=> (q[0] : 1'bx)) = (trstq);
        endspecify

    This is an edge-sensitive delay path description which says that when there is a
    negative edge on reset_b,
    then there is a delay of value trstq from 1'bx to q[0].

    Our lint tool did not accept this, saying that the syntax is legal, because of
    the + sign before =>,
    which according to the BNF is only allowed on simple delay paths descriptions,
    not on edge-sensitive path delay descriptions.

    They are correct about the BNF. The 1364 LRM also shows +=> only on simple
    paths. Same for Verilog-XL documentation.
    If you want to use the polarity symbol on edge-sensitive paths, you have to put
    it before the colon( +: or -: ) (not a smiley).

    The funny thing is that all 3 simulators that we have accept the code as written
    by our memory group,
    who are apparently used to writing it that way all the time.

    The lint tool vendor indicated that another simulator that he checked gave a
    warning.

    Can anyone explain this?

    Thanks,
    Shalom 

    --
Shalom Bresticker                        Shalom.Bresticker @freescale.com
Design & Verification Methodology                    Tel: +972 9  9522268
Freescale Semiconductor Israel, Ltd.                 Fax: +972 9  9522890
POB 2208, Herzlia 46120, ISRAEL                     Cell: +972 50 5441478

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