Re: errata/654: 14.2.3: specify block edge-sensitive path description with polarity

From: Steven Sharp (sharp@cadence.com)
Date: Thu Mar 03 2005 - 10:40:00 PST

  • Next message: Steven Sharp: "Re: errata/655: 2005D6, 7.1.6: ambiguities in instance array port connection rules"

    The following reply was made to PR errata/654; it has been noted by GNATS.

    From: Steven Sharp <sharp@cadence.com>
    To: etf-bugs@boyd.com, Shalom.Bresticker@freescale.com
    Cc:
    Subject: Re: errata/654: 14.2.3: specify block edge-sensitive path description with polarity
    Date: Thu, 3 Mar 2005 13:55:19 -0500 (EST)

    >But all 3 simulators that we have accept the code as written by our memory
     group,
    >who are apparently used to writing it that way all the time.
    >
    >Should this syntax be legal? What does it mean?
     
     I would guess that the simulators are completely ignoring the +. Even
     for simple delay path descriptions, it has no effect on the behavior of
     a simulator. The tools probably throw it away as soon as they see it,
     without worrying about what kind of path this is.
     
     Steven Sharp
     sharp@cadence.com
     



    This archive was generated by hypermail 2.1.4 : Thu Mar 03 2005 - 10:40:12 PST and
    sponsored by Boyd Technology, Inc.