From: Shalom.Bresticker@freescale.com
Date: Fri Apr 08 2005 - 04:23:36 PDT
The attached file contains the original proposal for $fullskew.
(Look for "fullskew".)
It should make more clear the intention.
In the example, it helps to think of CP and CPN as complementary signals,
independently generated, so that you don't know which will change first.
Sorry I don't have time today to go into this in more detail.
I'll try to write this up more fully tomorrow night.
Shalom
-- Shalom.Bresticker @freescale.com Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential Proprietary---------- Forwarded message ---------- Date: Wed, 13 Aug 97 20:46:11 MDT From: Steve Wadsworth <wadswort@poci.amis.com> To: 1364core@galaxy.nsc.com, ovi@netcom.com Subject: Asic Task Force issues for August 18th meeting
---------- X-Sun-Data-Type: text X-Sun-Data-Description: text X-Sun-Data-Name: text
Greetings,
I have included for your review four proposals we have passed and two that are in the final stages. The proposals that have passed the ATF committee are xpulse, fullskew,recrem, and removal. NTC (negative timing checks) and VCD (in postscript format) are included also for your review.
Also note that all completed issues are in the 1364 IR format.
See all of you at the meeting.
Steve Wadsworth
American Microsystems, Inc. Senior Staff Software Engineer wadswort@poci.amis.com Phone: (208) 234-6739 FAX : (208) 234-6795 ---------- X-Sun-Data-Type: default X-Sun-Data-Description: default X-Sun-Data-Name: xpulse_ir.txt X-Sun-Encoding-Info: uuencode
begin 600 xpulse_ir.txt M245%12 Q,S8T(%931R!)<W-U92!.=6UB97(Z($%41C\_/PH*0VQA<W-I9FEC M871I;VXZ(" @(" @(" @5&EM:6YG"@I)145%(#$S-C0@5F5R<VEO;CH@(" @ M("!)145%(#$S-C0G.3@*"E-U;6UA<GDZ"DET(&ES(&1E<VER960@=&\@:6UP M<F]V92!T:&4@<'5L<V4@9FEL=&5R:6YG(&-A<&%B:6QI='D@9F]R( I)145% M(#$S-C0@8V]M<&QI86YT('-I;75L871O<G,N("!&;W(@=&AE('-I;7!L:6-I M='D@;V8@=&AI<R!P<F]P;W-A;" *(E9E<FEL;V<B('-H86QL(&AE<F5A9G1E M<B!M96%N(&%L;" Q,S8T(&-O;7!L:6%N="!S:6UU;&%T;W)S+B @5&AE( IP M<F]P;W-A;"!C;W9E<G,@='=O('-E<&%R871E(&ES<W5E<R!W:71H(')E9V%R M9"!T;R!P=6QS92!F:6QT97)I;F<N"B @"E1H92!F:7)S="!I<W-U92!I<R!T M;R!P<F]V:61E('1H92!M;V1E;&5R('1W;R!M971H;V1S(&]F('!U;'-E( IF M:6QT97)I;F<Z("!/;BU$971E8W0@86YD($]N+45V96YT+B @3VXM179E;G0@ M:7,@=&AE(&UE=&AO9"!S=7!P;W)T960@"F)Y(&-U<G)E;G0@:6UP;&5M96YT M871I;VYS(&]F(%9E<FEL;V<@,3,V-"X@(%1H92!/;BU$971E8W0@;65T:&]D M( IA;&QO=W,@;6]R92!P97-S:6UI<VT@=VAE;B!F:6QT97)I;F<@<'5L<V5S M('1O('1H92!8('-T871E+"!P<F]D=6-I;F<@"F$@;&]N9V5R(%@@<F5G:6]N M+B @"@I4:&4@<V5C;VYD(&ES<W5E(&-O;F-E<FYS(&%N;VUA;&EE<R!A<W-O M8VEA=&5D('=I=&@@<V-H961U;&4@"F-A;F-E;&QA=&EO;B!F;W5N9"!I;B!C M=7)R96YT(%9E<FEL;V<@,3,V-"!I;7!L96UE;G1A=&EO;G,N("!38VAE9'5L M92 *8V%N8V5L;&%T:6]N(&]C8W5R<R!W:&5N(&YA<G)O=R!P=6QS97,@;W(@ M;F5A<FQY('-I;75L=&%N96]U<R *=')A;G-I=&EO;G,@;V-C=7(@870@=&AE M(&UO9&5L(&EN<'5T<RX*"E)E;&%T960@27-S=65S.B @(" @(" @($YO;F4* M4F5L979A;G0@3%)-(%-E8W1I;VYS.B @,3,L,30L,3<*2V5Y(%=O<F1S(&%N M9"!0:')A<V5S.B @/$E%144@,3,V-"!T97)M<SX*4')I;W)I='D@+2!3=6)M M:71T960Z(" @0W)I=&EC86P*(" @(" @(" @(" @(" @(" @(" @(" @0W)I M=&EC86P*(" @(" @(" @(" @(" @(" @(" @(" @26UP;W)T86YT"B @(" @ M(" @(" @(" @(" @(" @(" @($1E<VER86)L90H*4')I;W)I='D@(" @(" @ M(" @(" @(#$*"B @(" @(" @(" @(" @(" @(" @(" @(#$@(" @(" \5$8@ M87-S:6=N<RX^"B @(" @(" @(" @(" @(" @(" @(" @(#(*(" @(" @(" @ M(" @(" @(" @(" @(" @,PH)"2 @(" @(" @- H@(" @(" @(" @(" @(" @ M(" @(" @("!5;FMN;W=N(" @(" @(#Q!=71H;W(@87-S:6=N<RX^"@I#=7)R M96YT(%-T871U<SH@(" @("!41BU!<'!R;W9E9 H*(" @(" @(" @(" @(" @ M(" @(" @(" @4W5B;6ET=&5D(" @(" \075T:&]R(&%S<VEG;G,N/@H@(" @ M(" @(" @(" @(" @(" @(" @("!!;F%L>7IE9" @(" @(#Q41B!A<W-I9VYS M+CX*(" @(" @(" @(" @(" @(" @(" @(" @5$8M07!P<F]V960@(#Q41B!A M<W-I9VYS+CX*(" @(" @(" @(" @(" @(" @(" @(" @5E-'+4%P<')O=F5D M(" \5$8@87-S:6=N<RX^"B @(" @(" @(" @(" @(" @(" @(" @(%-U<&5R M8V5D960@(" @/%1&(&%S<VEG;G,N/@I3=7!E<G-E9&5D($)Y.B @(" @(" @ M("!.+T$*245%12!"86QL;W0@1&ES<&]S:71I;VXZ/$]N92!O9B!T:&4@9F]L M;&]W:6YG.CX*(" @(" @(" @(" @(" @(" @(" @(" @56YK;F]W;@H@(" @ M(" @(" @(" @(" @(" @(" @("!#;&]S960@*$%L;"!)<W-U97,@0V]M<&QE M=&5L>2!!9&1R97-S960I"B @(" @(" @(" @(" @(" @(" @(" @($)U9W,@ M1FEX960L($5N:&%N8V5M96YT<R!/=71S=&%N9&EN9R H3F\@5$8@27-S=65S M*0H@(" @(" @(" @(" @(" @(" @(" @("!3=7!E<G-E9&5D("A41B!)<W-U M97,@3W5T<W1A;F1I;F<I"D1I<W!O<VET:6]N(%)A=&EO;F%L93H@(#Q4;R!B M92!C;VUP;&5T960@8GD@=&AE(%1&/@I3=7!E<G-E9&5D($)Y.B @(" @(" @ M(" \<W5P97)C961I;F<@:7-S=64G<R!N=6UB97(^"@I$871E(%-U8FUI='1E M9#H@(" @(" @(" @,34@2G5L>2 Q.3DW"D%U=&AO<B!O9B!3=6)M:7-S:6]N M.B @("!3=&5V92!7861S=V]R=&@*075T:&]R)W,@069F:6QI871I;VXZ(" @ M($%M97)I8V%N($UI8W)O<WES=&5M<RP@26YC+@I!=71H;W(G<R!0;W-T($%D M9')E<W,Z(" @,C,P,"!"=6-K<VMI;B!29"X@4&]C871E;&QO($E$(#@S,C Q M"D%U=&AO<B=S(%!H;VYE($YU;6)E<CH@(" H,C X*2 R,S0M-C<S.0I!=71H M;W(G<R!&87@@3G5M8F5R.B @(" @*#(P."D@,C,T+38W.34*075T:&]R)W,@ M3F5T($%D9')E<W,Z(" @('=A9'-W;W)T0'!O8VDN86UI<RYC;VT*"BTM+2TM M+2TM+2TM+2TM+2TM+2TM+2TM"D1A=&4@06YA;'EZ960Z(" @(" @(" @(#$S M($%U9W5S=" Q.3DW"D%U=&AO<B!O9B!!;F%L>7-I<SH@(" @(%-T979E(%=A M9'-W;W)T: I2979I<VEO;B!.=6UB97(Z(" @(" @(" D4F5V:7-I;VXZ(#$N M," D"D1A=&4@3&%S="!2979I<V5D.B @(" @("1$871E.B Q.3DW+S X+S$S M"@H*1&5S8W)I<'1I;VX@;V8@4')O8FQE;0HM+2TM+2TM+2TM+2TM+2TM+2TM M+2TM"E1H92!F;VQL;W=I;F<@9&5T86EL960@9&5S8W)I<'1I;VX@=VEL;"!D M:7-C=7-S(&9U<G1H97(@=&AE(&YE960@9F]R( IO9F9E<FEN9R!/;BU$971E M8W0@<'5L<V4@9FEL=&5R:6YG+"!M;W)E(&1E=&%I;"!O;B!T:&4@<'5L<V4@ M"F-A;F-E;&QA=&EO;B!P<F]B;&5M+"!A;F0@82!D:7-C=7-S:6]N(&]F('1H M92!P=6QS92!C86YC96QL871I;VX@87,@"FET(')E;&%T97,@=&\@;75L=&EP M;&4@:6YP=71S(&]N('1H92!G871E+@H*3VXM1&5T96-T(&ES(&$@;65T:&]D M(&]F(&9I;'1E<FEN9R!P=6QS97,@=&\@=&AE(%@M<W1A=&4@=VAE<F5I;B!T M:&4@"E@M<W1A=&4@87!P96%R<R!I;6UE9&EA=&5L>2!U<&]N('1H92!O8V-U M<G)E;F-E(&]F('1H92!C;&]S:6YG(&5D9V4@"F]F('1H92!V:6]L871I;F<@ M:6YP=70@=')A;G-I=&EO;BX@(%1H92!8('-T871E(')E;6%I;G,@=6YT:6P@ M=&AE( IN;W)M86QL>2!C86QC=6QA=&5D(&1E;&%Y(&9O<B!T:&4@;F5W(&]U M='!U="!S=&%T92X@(%1H:7,@=VEL;"!M;W)E( IA8V-U<F%T96QY(')E9FQE M8W0@=&AE(&]U='!U="!C875S960@8GD@;F5A<FQY('-I;75L=&%N96]U<R!I M;G!U=',@"G1H870@<F5S=6QT(&EN('-C:&5D=6QI;F<@=&AE(&]U='!U="!E M=F5N=',@870@=&AE('-A;64@=&EM92X*"D]N+45V96YT(&ES(&$@;65T:&]D M(&]F(&9I;'1E<FEN9R!P=6QS97,@=VAE<F5I;B!T:&4@=')A;G-I=&EO;B!T M;R!8( IO8V-U<G,@869T97(@=&AE(&YO<FUA;&QY(&-A;&-U;&%T960@9&5L M87D@9F]R('1H92!O<FEG:6YA;&QY( IS8VAE9'5L960@=')A;G-I=&EO;BP@ M=VAI;&4@=&AE('1R86YS:71I;VX@9G)O;2!8(&]C8W5R<R!A9G1E<B!T:&4@ M"FYO<FUA;&QY(&-A;&-U;&%T960@9&5L87D@9F]R('1H92!N97<@;W5T<'5T M('-T871E+@H*"D].+41%5$5#5" M5E,M($].+45614Y4(%!53%-%($9)3%1% M4DE.1SH*"E=H96X@:70@:7,@9&5T97)M:6YE9"!T:&%T(&%N(&]U='!U="!P M=6QS92!S:&]U;&0@=')A;G-I=&EO;B!T;R!A;B *(E@B('-T871E(&1U92!T M;R!A;B!I;G!U="!P=6QS92!V:6]L871I;VXL('-O;64@05-)0R!V96YD;W)S M('!R969E<B *;W5T<'5T<R!B92!S8VAE9'5L960@:6UM961I871E;'D@*$]N M7T1E=&5C="DL(&EN<W1E860@;V8@869T97(@=&AE( IT<F%N<VET:6]N86P@ M9&5L87D@*$]N7T5V96YT*2X@($-U<G)E;G1L>2 Q,S8T(&-O;7!L:6%N="!S M:6UU;&%T;W)S( IS=7!P;W)T(&]N;'D@3VXM179E;G0N("!6:71A;"!#;VUP M;&EA;G0@5DA$3"!S:6UU;&%T;W)S(&-U<G)E;G1L>2 *;V9F97(@05-)0R!6 M96YD;W)S('1H92!C:&]I8V4@;V8@<V5L96-T:6YG(&5I=&AE<B!M;V1E(&9O M<B!T:&5I<B *;&EB<F%R:65S+B *"D9I9W5R92 Q('5S97,@82!S:6UP;&4@ M8G5F9F5R('=I=&@@87-Y;6UE=')I8R!R:7-E+V9A;&P@=&EM97,@86YD( IP M=6QS92!L:6UI=',@97%U86P@=&\@=&AE(&1E;&%Y('1O(&EL;'5S=')A=&4@ M=&AI<R!B96AA=FEO<BX@($%N( IO=71P=70@=V%V969O<FT@(&ES('-H;W=N M(&9O<B!B;W1H($]N+41E=&5C="!A;F0@3VXM179E;G0N"@H@(" @(" @(" @ M(" @(" @(" @(" @(" @(" @(" @("!R:7-E+V9A;&P*(" @(" @(" @(" @ M(" @(" @(" @(" @(" @(" @(" @(" @"B @(" @(" @(" @(" @(" @(" @ M(" @(" @(" @?%P@(#0O-@H@(" @(" @(" @(" @24X@(" M+2TM+2TM+2TM M+7P@/BTM+2TM+2TM+2TM($]55 H@(" @(" @(" @(" @(" @(" @(" @(" @ M(" @('PO"@H@(" @(" @(" @(" @(" @(" @(" @(" @*RTM*PH@(" @(" @ M(" @(" @(" @(" @(" @(" @?" @? H@(" @(" @(" @(" @24X@(" M+2TM M+2TM*R @*RTM+2TM+2TM+2TM+2TM+2TM+0H@(" @(" @(" @(" @(" @(" @ M(" @(" Q," @,3(*(" @(" @(" @(" @(" @(" @(" @(" @(" @(" @(" K M+2TM+2L*(" @(" @(" @(" @(" @(" @(" @(" @(" @(" @("!\6%A86'P* M("!/550@*$]N+45V96YT*2 @+2TM+2TM+2TM+2TM+2TK(" @("LM+2TM+2TM M+0H@(" @(" H5F5R:6QO9RD@(" @(" @(" @(" @(" @,30@(" Q. H*(" @ M(" @(" @(" @(" @(" @(" @(" @(" @("LM+2TM+2TM+2L*(" @(" @(" @ M(" @(" @(" @(" @(" @(" @('Q86%A86%A86'P*("!/550@*$]N+41E=&5C M="D@+2TM+2TM+2TM+2L@(" @(" @("LM+2TM+2TM+0H@(" @(" @(" @(" @ M(" @(" @(" @(" @(" @,3(@(" @(" @,3@*(" @(" @(" @(" @(" @(" @ M(" @(" @( H@(" @(" @(" @(" @1FEG=7)E(#$Z($].($1%5$5#5" M5E,@ M+2!/3B!%5D5.5 D*"@H*4T-(14153$4@0T%.0T5,3$%424]..@H*1FEG=7)E M(#(@<VAO=W,@82!N87)R;W<@<'5L<V4@;VX@=&AE(&EN<'5T(&]F('1H92!B M=69F97(@=&AA=" *=FEO;&%T97,@=&AE('!U;'-E('=I9'1H+B @5&AE(&)U M9F9E<B!H87,@87-Y;6UE=')I8V%L(')I<V4O9F%L;" *9&5L87ES('=H:6-H M(&ES('9E<GD@8VAA<F%C=&5R:7-T:6,@;V8@05-)0R=S+"!E<W!E8VEA;&QY M(&=A=&4@"F%R<F%Y<RX@5&AE(&9A;&QI;F<@961G92!O9B!T:&4@<'5L<V4@ M<V-H961U;&5S(&%N(&5V96YT(#8@=6YI=',@"FQA=&5R(&%T('1H92!P;VEN M="!M87)K960@8GD@(D$B+B @3VYE('1I;64@=6YI="!L871E<B!T:&4@<'5L M<V4@"G)E='5R;G,@=&\@(C$B('=H:6-H('-C:&5D=6QE<R!A;B!E=F5N=" T M('5N:71S(&QA=&5R(&UA<FME9"!B>2!P;VEN=" *(D(B+B @5&AI<R!S96-O M;F0@<V-H961U;&4@;VX@=&AE(&]U='!U="!I<R!F;W(@82!T:6UE('!R:6]R M('1O('1H92 *86QR96%D>2!E>&ES=&EN9R!S8VAE9'5L92X*"D-U<G)E;G1L M>2 Q,S8T(%9E<FEL;V<@<VEM=6QA=&]R<R!I9VYO<F4@8F]T:"!E=F5N=',@ M87,@<VAO=VX@8GD@=&AE( IW879E9F]R;2!/5510550@*%9E<FEL;V<I+B @ M5&AE(&]T:&5R('1W;R!O=71P=70@=V%V969O<FUS(")/;BU%=F5N="(@"F%N M9" B3VXM1&5T96-T(B!S:&]W('1W;R!V86QI9"!R97-P;VYS97,@9F]R('1H M92!S:6UU;&%T;W(@9&5P96YD:6YG( IO;B!T:&4@;6]D96QE<G,@8VAO:6-E M(&9O<B!P=6QS92!F:6QT97)I;F<N("!.96ET:&5R($]N+45V96YT(&]R($]N M+0I$971E8W0@<')O=FED92!A(")C;W)R96-T(B!A;G-W97(@*'1H870@=V]U M;&0@<F5Q=6ER92!3<&EC92 *<VEM=6QA=&EO;BDL('-O('1H92!M;V1E;&5R M(&UU<W0@<V5L96-T('1H92!M971H;V0@8F%S960@;VX@=&AE:7(@"FQI8G)A M<GD@8VAA<F%C=&5R:7IA=&EO;B!A;F0@8F5S="!J=61G96UE;G0N(" *"@H* M"B @(" @(" @(" @(" @(" @(" @(" @(" @(" @(" @(')I<V4O9F%L; H* M(" @(" @(" @(" @(" @(" @(" @(" @(" @("!\7" @-"\V"B @(" @(" @ M(" @("!)3B @("TM+2TM+2TM+2TM?" ^+2TM+2TM+2TM+2TM($]55 H@(" @ M(" @(" @(" @(" @(" @(" @(" @(" @('PO"@H@(" @(" @(" @(" @(" @ M(" M+2TM+2TM*R K+2TM+2TM+2TM+2TM+2TM+2TM+2T*(" @(" @(" @(" @ M(" @(" @(" @(" @('P@?" @(" @("!>(%X*(" @(" @(" @(" @($E.(" @ M(" @(" @("LM*R @(" @("!\('P*(" @(" @(" @(" @(" @(" @(" @(" @ M,3 @,3$@(" @("!"($$*"B @(" @(" @(" @( H@($]55" H5F5R:6QO9RD@ M(" M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM"@H*(" @(" @(" @ M(" @(" @(" @+2TM+2TM+2TM+2TM+2TM+2TK("LM+2TM+2TM+2TM+0H@(" @ M(" @(" @(" @(" @(" @(" @(" @(" @(" @(" @('Q8? H@($]55" H3VXM M179E;G0I(" @(" @(" @(" @(" @(" @("LM*PH@(" @(" @(" @(" @(" @ M(" @(" @(" @(" @(" @(" @,34@,38*"B @(" @(" @(" @(" @(" @("TM M+2TM+2TM+2L@(" @(" @(" K+2TM+2TM+2TM+2T*(" @(" @(" @(" @(" @ M(" @(" @(" @(" @?%A86%A86%A86'P*("!/550@*$]N+41E=&5C="D@(" @ M(" @(" @*RTM+2TM+2TM+2L*(" @(" @(" @(" @(" @(" @(" @(" @(" Q M,2 @(" @(" @(#$V"@H@(" @($9I9W5R92 R.B!#=7)R96YT($5V96YT(&-A M;F-E;&QA=&EO;B!P<F]B;&5M(&%N9"!C;W)R96-T:6]N"0H*"D9R;VT@82!D M:6=I=&%L('-I;75L871I;VX@<&]I;G0@;V8@=FEE=RP@:70@=V]U;&0@<V5E M;2!T:&%T('-I;F-E('1H92 *<'5L<V4@:7,@;F%R<F]W(&%N9"!T:&4@<V5C M;VYD('-C:&5D=6QE9"!E=F5N=" B0B(@<')E8V5D97,@=&AE(&YO;BT*;6%T M=7)E9"!E=F5N=" B02(@=&AA="!B;W1H(&-A;B!B92!I9VYO<F5D+B @2&]W M979E<BP@:6X@<W!I8V4@86YD( IA8W1U86P@<VEL:6-O;B!T:&5R92!I<R!A M;B!A;6)I9W5O=7,@<F5G:6]N(&)E='=E96X@=&AE('1W;R!E=F5N=',@"G1H M870@:&%S(&%N('5N:VYO=VX@=F%L=64@<VEN8V4@=&AE<V4@961G97,@87)E M(&YO="!S:&%R<"P@8G5T(&AA=F4@"G-O;64@;F]N;&EN96%R(')A;7 @=&EM M92!T;R!R96%C:"!T:&4@86-T=6%L(&1E;&%Y(&YU;6)E<BX@($1U<FEN9R * M=&AI<R!N;VYL:6YE87(@<F5G:6]N(&ET(&AA<R!T:&4@<&]T96YT:6%L('1O M('!R;V1U8V4@82!S;6%L;"!N87)R;W<@"G!U;'-E(&%N9"!C875S92!A;B!E M=F5N="!O;B!A(&1I<F5C="!A8W1I;VX@<VEG;F%L+B @5&AU<RP@<VEN8V4@ M=&AI<R *<&]T96YT:6%L(&5X:7-T<RP@=&AE('-I;75L871O<B!M=7-T('!R M;V1U8V4@86X@(E@B('1O(&EN<W5R92!T:&%T( IT:&4@8V]N9&ET:6]N(&ES M(&-A=6=H="!A;F0@;F]T:6-E9"X*"@I.14%23%D@4TE-54Q404Y%3U53(%-7 M251#2$E.1R!)3E!55%,@*$1)1D9%4D5.5"!%5D5.5"!424U%*3H*"E1H:7,@ M<W!E8VEA;"!C;VYD:71I;VX@87)I<V5S('=H96X@='=O(&EN<'5T<R!A<G)I M=F4@870@;F5A<FQY('1H92 *<V%M92!T:6UE("AC;&]S97(@=&]G971H97(@ M:6X@=&EM92!T:&%N('1H92!D:69F97)E;F-E(&EN(&1E;&%Y<RDN(" *5&AI M<R!C;VYD:71I;VX@:7,@<VEM:6QA<B!T;R!T:&4@;VYE(&1E<V-R:6)E9"!A M8F]V92!I;B!T:&4@8G5F9F5R( IC87-E(&5X8V5P="!M=6QT:7!L92!S:6=N M86QS(&%R92!I;G9O;'9E9"X@("!&:6=U<F4@,R!S:&]W<R!T:&4@"G=A=F5F M;W)M(&9O<B!A(#(@:6YP=70@3D%.1"!G871E('=H97)E(")!(B!I<R B,2(@ M86YD(")"(B!I<R B,"(N("!!=" *=&EM92 Q," B0B(@;6%K97,@=&AE("(P M+3XQ(B!T<F%N<VET:6]N('=H:6-H('-C:&5D=6QE<R!T:&4@;W5T<'5T('1O M( IM86ME('1H92 B,2T^,"(@=')A;G-I=&EO;B!A="!T:6UE(#(T+B @070@ M=&EM92 Q,BP@(D$B('1R86YS:71I;VYS( HB,2T^,"(@<V-H961U;&EN9R!T M:&4@;W5T<'5T('1O('1R86YS:71I;VX@9G)O;2 B,"T^,2(@870@=&EM92 R M,BX@( I4:&4@87)R;W=S(&]N('1H92!S:6=N86QS(")!(B!A;F0@(D(B(&EN M9&EC871E('=H96X@=&AE(&]U='!U="!E=F5N=" *:7,@<V-H961U;&5D(&9O M<B!T:&%T(&-H86YG92!I;B!T:&4@:6YP=70N(" *"@D)"0D)4FES92H)1F%L M;"H*"0D)"4$M/E$),3 ),3 *"0D)"4(M/E$),30),30*"@H@(" @(" @(" @ M(" @(" @("TM+2TM*R @(" @(" @('P@(" @(" @(" @(" @(" @(" @(" @ M(" @"B @(" @(" @(" @($$@(" @(" @("!\(" @(" @(" @5B @(" @(" @ M(" @(" @(" @(" @(" @(" @(" @( H@(" @(" @(" @(" @(" @(" @(" @ M*RTM+2TM+2TM+2TM+2TM+2TM+2TM+2T@(" @(" *(" @(" @(" @(" @(" @ M(" @(" @,3(@(" @(" @(" @(" @(" @(" @(" @(" @(" @(" @(" *(" @ M(" @(" @(" @(" @(" @(" K+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM(" @ M(" @(" @(" @( H@(" @(" @(" @("!"(" @(" @('P@(" @(" @(" @(" @ M7B @( H@(" @(" @(" @(" @(" @("TM+2L@(" @(" @(" @(" @?" @( H@ M(" @(" @(" @(" @(" @(" @(#$P(" @(" @(" @(" @(" @(" @"@H*(" @ M(" @(" @($]55" @(" M+2TM+2TM+2TM+2TM+2TM+2LM+2TM+2TM+2TM"B @ M(" @(" @(" @*%9E<FEL;V=83"D@(" @(" @(" @(" @"B @(" @(" @(" @ M(" @(" @(" @(" @(" @(" @(" @(" @"@H@(" @(" @(" @3U54(" @("TM M+2TM+2TM+2TM+2TM+2LM*RTM+2TM+2TM+2T@(" @(" @(" @(" @(" @"B @ M(" @(" @(" H3VXM179E;G0I(" @(" @(" @(" @?%A\(" @(" @(" @(" @ M(" *(" @(" @(" @(" @(" @(" @(" @(" @(" @(" @(" K+2L@(" @"B @ M(" @(" @(" @(" @(" @(" @(" @(" @(" @(" R,B R-" @(" @(" @( H* M(" @(" @(" @(" @(" @(" M+2TM+2LM+2TM+2TM+2TM+2LM+2TM+2TM+2TM M(" @(" @(" @"B @(" @(" @(" @(" @(" @(" @("!\6%A86%A86%A86%A\ M(" @(" @(" @"B @(" @(" @("!/550@(" @(" @(" K+2TM+2TM+2TM+2TK M"B @(" @(" @(" H3VXM1&5T96-T*2 Q,B @(" @(" @(" R-" @(" @(" @ M"@H*(" @("!&:6=U<F4@,SH)3D%.1"!G871E('=I=&@@;F5A<FQY('-I;75L M=&%N96]U<R!I;G!U="!S=VET8VAI;F<@"B @(" @(" @(" @(" @("!W:&5R M92!O;F4@979E;G0@:7,@<V-H961U;&5D('!R:6]R('1O(&%N;W1H97(@=&AA M=" *(" @(" @(" @(" @(" @(&AA<R!N;W0@;6%T=7)E9"X*"@H*4VEN8V4@ M=&AE('-E8V]N9"!I;G!U=" H(D$B*2!H87,@8V%U<V5D(&%N(&5V96YT('1O M(&]C8W5R(&]N('1H92 *;W5T<'5T('!R:6]R('1O('1H92!O;F4@86QR96%D M>2!S8VAE9'5L960@9G)O;2!T:&4@(D(B('1R86YS:71I;VXL( IT:&4@;W5T M<'5T(&YE961S('1O(&AA=F4@86X@(E@B(&1U<FEN9R!T:&4@=6YC97)T86EN M='D@<F5G:6]N('-I;F-E( II="!I<R!U;FMN;W=N(&]N('1H92!A8W1U86P@ M<W1A=&4@;V8@=&AE(&]U='!U="!B971W965N('1H92!T=V\@"F]U='!U="!E M=F5N=',N"@I)9B!T:&4@:6YP=70@979E;G1S(&-A=7-E('1H92!O=71P=70@ M=&\@=')A;G-I=&EO;B!I;B!T:&4@<V%M92 *9&ER96-T:6]N('1H96X@=&AE M(")8(B!S=&%T92!I<R!I9VYO<F5D('-I;F-E(&ET(&ES(&IU<W0@82!T:6UI M;F<@"F1I9F9E<F5N8V4@<F%T:&5R('1H86X@86X@979E;G0@=&AA="!C875S M97,@=&AE(&]U='!U="!T;R!C<F5A=&4@82 *;6]M96YT87)I;'D@<'5L<V4N M(" )"2 @"0H*3D5!4DQ9(%-)355,5$%.14]54R!35TE40TA)3D<@24Y05513 M("A304U%($5614Y4(%1)344I.@H@(" @(" @(" @(" @(" @"0I&:6=U<F4@ M-"!S:&]W<R!T:&4@<F5S=6QT(&]F('1H92!N96%R;'D@<VEM=6QT86YE;W5S M(&EN<'5T(&5V96YT<R *8V%U<VEN9R!O=71P=70@979E;G1S('1O(&)E('-C M:&5D=6QE9"!A="!T:&4@<V%M92!T:6UE+@H*"@D)4FES92H)1F%L;"H*"4$M M/E$),3 ),3 *"4(M/E$),30),30*"@H@(" @(" @(" @(" @(" @("TM+2TM M+2TM+2TK(" @(" @(" @?" @(" @(" @(" @(" @(" @(" @(" @"B @(" @ M(" @(" @($$@(" @(" @(" @(" @('P@(" @(" @("!6(" @(" @(" @(" @ M(" @(" @(" @(" @(" @(" @"B @(" @(" @(" @(" @(" @(" @(" @(" @ M("LM+2TM+2TM+2TM+2TM+2TM+2TM+2 @(" @(" @"B @(" @(" @(" @(" @ M(" @(" @(" @(" @(#$T(" @(" @(" @(" @(" @(" @(" @(" @(" @(" @ M(" @"B @(" @(" @(" @(" @(" @(" @(" @*RTM+2TM+2TM+2TM+2TM+2TM M+2TM+2TM+2 @(" @(" @(" @(" *(" @(" @(" @(" @0B @(" @(" @("!\ M(" @(" @(" @(" @(%X@(" *(" @(" @(" @(" @(" @(" M+2TM+2TK(" @ M(" @(" @(" @('P@(" *(" @(" @(" @(" @(" @(" @(" @(" Q," @(" @ M(" @(" @(" @(" @( H*(" @(" @(" @($]55" @(" M+2TM+2TM+2TM+2TM M+2TM+2TM+2LM+2TM+2TM+2TM+0H@(" @(" @(" @("A697)I;&]G6$PI(" @ M(" @(" @(" @(" @(" @"B @(" @(" @(" @(" @(" @(" @(" @(" @(" @ M(" @(" @(" @(" @(" @(" @(" @"@H@(" @(" @(" @3U54(" @("TM+2TM M+2TM+2TM+2TM+2TM+2TM*RTM+2TM+2TM+2TM(" @"B @(" @(" @(" H3VXM M179E;G0I(" @(" @(" @(" @(" @("!\(" @(" @(" @(" @(" *(" @(" @ M(" @(" @(" @(" @(" @(" @(" @(" @(" @(" @("L@(" @(" @(" @"B @ M(" @(" @(" @(" @(" @(" @(" @(" @(" @(" @(" @(" R-" @(" @(" @ M( H*(" @(" @(" @(" @(" @(" M+2TM+2TM+2TM*RTM+2TM+2TM+2LM+2TM M+2TM+2TM+0H@(" @(" @(" @(" @(" @(" @(" @(" @("!\6%A86%A86%A8 M?" @(" @(" @( H@(" @(" @(" @3U54(" @(" @(" @(" @(" K+2TM+2TM M+2TM*R @(" @(" @(" @( H@(" @(" @(" @*$]N+41E=&5C="D@(" @(" Q M-" @(" @(" @,C0@(" @(" @( H*(" @("!&:6=U<F4@-#H@,B!);G!U="!. M04Y$(&=A=&4@=VET:"!N96%R;'D@<VEM=6QT86YE;W5S(&EN<'5T('-W:71C M:&EN9PH@(" @(" @(" @(" @=VET:"!O=71P=70@979E;G0@<V-H961U;&5D M(&%T('-A;64@=&EM92X)"@H*26X@=&AI<R!C87-E(")/;BU%=F5N="(@;6]D M92!M871C:&5S('1H92!C=7)R96YT(%9E<FEL;V<@8F5H879I;W(@86YD( ID M;V5S(&YO="!R969L96-T('1H870@=&AE(&5V96YT(&]C8W5R<F5D+B @5&AI M<R!I<R!B96-A=7-E(&)O=&@@;W5T<'5T( IE=F5N=',@;V-C=7(@870@=&AE M('-A;64@=&EM92!S;R!N;R B9&5L=&$B('=I=&@@86X@(E@B(&-A;B!B92!S M:&]W;BX@( I4:&ES(&ES(&%N;W1H97(@<F5A<V]N(&ET(&ES(&YE8V5S<V%R M>2!T;R!O9F9E<B!T:&4@(D]N+41E=&5C="(@;6]D92 *<V\@=&AE(&UO9&5L M(&1E=F5L;W!E<B!C86X@<F5F;&5C="!T:&ES(&)E:&%V:6]R(&EF(&1E<VER M960N"@D)"E1O(&-O;7!L>2!W:71H('1H:7,@;F5W(')E<75I<F5M96YT(%9E M<FEL;V<@,3,V-"!S:6UU;&%T;W)S('=O=6QD(&AA=F4@"G1O(&-H96-K(&9O M<B!A;B!O=71P=70@<V-H961U;&4@96%C:"!T:6UE(&%N(&EN<'5T('1R86YS M:71I;VYE9"X@($EF( IA;B!O=71P=70@<V-H961U;&4@86QR96%D>2!E>&ES M=&5D+"!A;F0@:68@=&AE(&EN<'5T)W,@9&5L87D@=VAE;B *861D960@=&\@ M8W5R<F5N="!S:6UU;&%T:6]N('1I;64@<F5S=6QT960@:6X@82!T:6UE(&QE M<W,@=&AA;B!T:&4@"F-U<G)E;G0@<V-H961U;&5D(&]U='!U="P@=&AE;B!A M('-C:&5D=6QE('1O(%@@870@=&AE(&QE<W-E<B!T:6UE( IW;W5L9"!H879E M('1O(&)E('!L86-E9"!O;B!T:&4@;W5T<'5T+B @5&AE(&5X:7-T:6YG('-C M:&5D=6QE(&%T('1H92 *;&%T97(@=&EM92!W;W5L9"!B92!M86EN=&%I;F5D M(&%S(&ES+@H*3W1H97(@<VEG;F]F9B!Q=6%L:71Y('-I;75L871O<G,@<W5C M:"!A<R!)2T]3(&1O(')E9FQE8W0@=&AI<R *8V]N9&ET:6]N(&-O<G)E8W1L M>2X@(%-I;F-E(%9E<FEL;V<G<R!C=7)R96YT(&)E:&%V:6]R(&ES($]N+45V M96YT+"!I;B *861D:71I;VX@=&\@8V]R<F5C=&EN9R!T:&ES(&)E:&%V:6]R M+"!697)I;&]G(#$S-C0@=V]U;&0@;F5E9"!T;R!O9F9E<B *3VXM1&5T96-T M(&UO9&4N(" *"E9I=&%L($-O;7!L:6%N="!62$1,('-I;75L871O<G,@8W5R M<F5N=&QY(&]F9F5R($%324,@;6]D96QE<G,@=&AE( IC:&]I8V4@;V8@<V5L M96-T:6YG(&5I=&AE<B!/;BU$971E8W0@;W(@3VXM179E;G0@;6]D92!F;W(@ M=&AE:7(@"FQI8G)A<FEE<RX@"@H*4')O<&]S960@4F5S;VQU=&EO;@HM+2TM M+2TM+2TM+2TM+2TM+2TM"@I'14Y%4D%,(%)53$53"DEN('1H92!C87-E(&]F M(&UU;'1I<&QE(&YE9V%T:79E('!R965M<'1I=F4@979E;G1S+"!T:&4@(E@B M(')E9VEO;B!S:&%L;" *97AT96YD('1O('1H92!E87)L:65S="!S8VAE9'5L M960@<')E96UP=&EV92!E=F5N="!A;F0@8V]N=&EN=64@=&\@=&AE"FQA=&5S M=" H:6X@=&EM92D@<V-H961U;&5D(&5V96YT('=H96X@;F5G871I=F4@<')E M96UP=&EO;B!F:7)S="!O8V-U<F5D+@H@"D-/34U!3D0@3$E.12!/4%1)3TY3 M.@I&;W5R(&YE=R!P;'5S(&]P=&EO;G,@87)E(&YE961E9"P@86QT:&]U9V@@ M=&AE(&YA;65S(&%N9"!W:&5T:&5R('1H97D@"F%R92!P;'5S(&]R(&UI;G5S M(&]P=&EO;G,@9&5P96YD<R!O;B!T:&4@141!(%9E;F1O<BX@(%1H92!O<'1I M;VYS(&%R92 *87,@9F]L;&]W<SH*"C$N("MS:&]W7V-A;F-E;&5D7V4@(" @ M+2!4=7)N<R!O;B!S:&]W8V%N8V5L960@(E@B('!U;'-E(&9I;'1E<FEN9PH@ M(" K;F]S:&]W7V-A;F-E;&5D7V4@("T@5'5R;G,@;V9F('-H;W=C86YC96QE M9" M($-U<G)E;G0@5F5R:6QO9UA,(&)E:&%V:6]R(" @(" *0V%U<V5S('-P M96-I9GD@<&%T:"!O=71P=71S('1O('5S92!T:&4@6"!S=&%T92!T;R!I;F1I M8V%T92!T:&4@"G!R97-E;F-E(&]F(&-A;F-E;&5D('-C:&5D=6QE<RX@(%1H M92!D969A=6QT(&ES(&YO<VAO=U]C86YC96QE9%]E( ID:7-P;&%Y(&UO9&4@ M=VAI8V@@:7,@=&AE(&-U<G)E;G0@5F5R:6QO9UA,(&)E:&%V:6]R+@H*,BX@ M*W!U;'-E7V5?<W1Y;&5?;VYE=F5N=" @("T@57-E<R!O;BUE=F5N=" @;65T M:&]D(&]F('!U;'-E(&AA;F1L:6YG"B @("MP=6QS95]E7W-T>6QE7V]N9&5T M96-T(" M(%5S97,@;VXM9&5T96-T(&UE=&AO9"!O9B!P=6QS92!H86YD;&EN M9PH*5&AI<R!A;&QO=W,@=&AE('5S97(@=&\@9VQO8F%L;'D@<V5L96-T('=H M:6-H(&1E=&5C=&EO;B!M971H;V0@:&4@"G=A;G1S('1O('5S92X@(%1H92!D M969A=6QT(&UO9&4@9F]R('!U;'-E7V5?<W1Y;&4@:7,@(F]N+65V96YT(B!W M:&EC:" *:7,@=&AE(&-U<G)E;G0@5F5R:6QO9UA,(&)E:&%V:6]R+B @5&AE M<V4@<&QU<R!O<'1I;VYS('-H;W5L9"!B92 *8VAE8VME9"!O;F-E(&1U<FEN M9R!S:6UU;&%T:6]N(&EN:71I86QI>F%T:6]N+"!S971T:6YG(&=L;V)A;',@ M=&AA=" *8V%N(&QA=&5R(&)E(&-H96-K960@8GD@=&AE('-C:&5D=6QI;F<@ M8V]D92X@268@82!S879E+W)E<W1A<G0@"F9E871U<F4@97AI<W1S(&9O<B!T M:&4@<VEM=6QA=&]R+"!T:&4@9VQO8F%L('9A;'5E<R!M=7-T(&)E( IP<F5S M97)V960N("!3964@<V5C=&EO;B U+C0@9F]R('!R96-E9&5N8V4@;W)D97(N M( H*4UE35$5-(%1!4TL@3U!424].4PH*3F5W('-Y<W1E;2!T87-K<R!A<F4@ M;F5E9&5D('1O(&EN9F]R;2!T:&4@8V]M<&EL97(@:&]W('1O('!E<F9O<FT@ M=&AE( IP=6QS92!F:6QT97)I;F<N("!4:&4@9F]L;&]W:6YG('-Y<W1E;2!T M87-K<R!A;&QO=R!T:&4@;6]D96QE<B!T:&4@"F-A<&%B:6QI='D@=&\@9&5F M:6YE('1H92!C86YC96QE9"!E=F5N="!D:7-P;&%Y(&UO9&4@*&]N(&]R(&]F M9BD@86YD( IT:&4@<W1Y;&4@;V8@=&AE('!U;'-E("AO;BUE=F5N="!O<B!O M;BUD971E8W0I+B @5&AE(&1I<V%B;&4@<WES=&5M( IT87-K<R!A<F4@;F]T M(')E<75I<F5D('-I;F-E('1H92!O=71P=71S('1A:V4@;VX@=&AE(&1E9F%U M;'0@=F%L=65S( II9B!N;VYE(&%R92!D969I;F5D+B @06YY('!A=&@@=&AA M="!A<F4@=&\@=7-E('1H97-E(&1E9F%U;'0@=F%L=65S( IN965D('1O(&)E M('!L86-E9"!P<FEO<B!T;R!A;GD@<WES=&5M('1A<VL@9&5C;&%R871I;VXN M"@I)9B!N;R!S>7-T96T@=&%S:R!I<R!S<&5C:69I960@=&AE(&-O;7!I;&5R M('=I;&P@=&AE;B!R969E<B!T;R!T:&4@"F-O;6UA;F0@;&EN92!O<'1I;VX@ M9F]R(&ET)W,@8F5H879I;W(N("!)9B!N;R!C;VUM86YD(&QI;F4@;W!T:6]N M(&ES( IG:79E;B!T:&4@8F5H879I;W(@:7,@=&AE(%9E<FEL;V=83"!D969A M=6QT('=H:6-H(&ES(&YO<VAO=V-A;F-E;&QE9" *9F]R('1H92!D:7-P;&%Y M(&UO9&4@86YD(&]N+65V96YT(&9O<B!T:&4@<'5L<V5S='EL92X@(%1H92!S M8V]P92!O9B *=&AE('-Y<W1E;2!T87-K(&ES('1H92!S<&5C:69Y(&)L;V-K M+B @4V5E('-E8W1I;VX@-2XT(&9O<B!M;W)E( ID971A:6P@;VX@=&AE(&5V M86QU871I;VX@<')E8V5D96YC92!O<F1E<BX*"C$N(%-E='1I;F<@=&AE('-H M;W=C86YC96QL960@;W!T:6]N<R!F;W(@96ET:&5R('1U<FYI;F<@:70@;VX@ M;W(@;V9F( IH879E('1W;R!P;W-S:6)L92!F;W)M871S+B @5&AE(&UO<W0@ M9V5N97)A;"!H87,@;F\@<&%T:',@"G-P96-I9FEE9"!A;F0@87!P;&EE<R!T M;R!A;&P@;W5T<'5T<RX@(%1H92!O=&AE<B!A;&QO=W,@=&AE('5S97(@"G1O M('-P96-I9FEC86QL>2!S<&5C:69Y('1H92!O=71P=70@=&AA="!I<R!E9F9E M8W1E9"!B>2!T:&4@<WES=&5M( IT87-K+@H*(" D<VAO=V-A;F-E;&QE9#L@ M+5-E="!O=71P=70H<RD@:6X@;6]D=6QE('1O('-H;W<@8V%N8V5L960@<V-H M961U;&5S"B @)'-H;W=C86YC96QL960@6R@\<&%T:%]O=71P=70^*5T[("T@ M4V5T("AP871H*2 B6"(@9&ES<&QA>2!M;V1E(&]N"B *(" D;F]S:&]W8V%N M8V5L;&5D.R M4V5T(&]U='!U="AS*2!I;B!M;V1U;&4@=&\@:6=N;W)E(&-A M;F-E;&5D('-C:&5D=6QE<PH@("1N;W-H;W=C86YC96QL961;*#QP871H7V]U M='!U=#XI73LM(%-E=" H<&%T:"D@(E@B(&1I<W!L87D@;6]D92!O9F8*"@HR M+B!3971T:6YG('1H92!P=6QS92 G92<@<W1Y;&4@96ET:&5R(&EN(&]N+61E M=&5C="!O<B!O;BUE=F5N="!H87,@"G1W;R!P;W-S:6)L92!F;W)M871S+B @ M5&AE(&UO<W0@9V5N97)A;"!H87,@;F\@<&%T:',@<W!E8VEF:65D(&%N9" * M87!P;&EE<R!T;R!A;&P@;W5T<'5T<RX@(%1H92!O=&AE<B!A;&QO=W,@=&AE M('5S97(@=&\@<W!E8VEF:6-A;&QY( IS<&5C:69Y('1H92!O=71P=70@=&AA M="!I<R!E9F9E8W1E9"!B>2!T:&4@<WES=&5M('1A<VLN"@H@("1P=6QS97-T M>6QE7V]N979E;G0[(" M(%-E="!/=71P=70H<RD@:6X@;6]D=6QE('1O(&]N M+65V96YT(&9I;'1E<FEN9PH@("1P=6QS97-T>6QE7V]N979E;G0@6R@\<&%T M:%]O=71P=70^*5T[(" M(%-E=" H<&%T:"D@;VXM979E;G0*"B @)'!U;'-E M<W1Y;&5?;VYD971E8W0[("T@4V5T($]U='!U="AS*2!I;B!M;V1U;&4@=&\@ M;VXM9&5T96-T(&9I;'1E<FEN9PH@("1P=6QS97-T>6QE7V]N9&5T96-T(%LH M/'!A=&A?;W5T<'5T/BE=.R @+2!3970@*'!A=&@I(&]N+61E=&5C=" *"@I3 M65-414T@5$%32R!%6$%-4$Q%4PH*0V%N8V5L960@<V-H961U;&4@9&ES<&QA M>0H*5&AE(&9O;&QO=VEN9R!E>&%M<&QE<R!D97-C<FEB92!T:&4@=F%R:6]U M<R!U<V5S(&]F('1H92!S:&]W8V%N8V5L;&5D( IS>7-T96T@=&%S:R!T;R!C M;VYT<F]L('1H92!B96AA=FEO<B!O9B B86QL(B!O<B B<W!E8VEF:6,B('!A M=&AS(&]F('1H92 *<W!E8VEF>2!B;&]C:RX@($%S(&1E<V-R:6)E9"!A8F]V M92!T:&4@9&5F875L="!D:7-P;&%Y(&UO9&4@:7,@"FYO<VAO=V-A;F-E;&QE M9"X@(%-I;F-E('1H92!D969A=6QT(')U;&4@:7,@875T;VUA=&EC86QL>2!A M<'!L:65D('1O( IA;&P@<&%T:',@:6X@=&AE(&%B<V5N8V4@;V8@82!S>7-T M96T@=&%S:RP@;F\@(F1E9F%U;'0B('-Y<W1E;2!T87-K(&ES( IR97%U:7)E M9"X@(%!A=&AS('1H870@87)E('1O('5S92!T:&4@9&5F875L=" H;VXM979E M;G0I(&YE960@=&\@8F4@"G!L86-E9"!P<FEO<B!T;R!A;GD@<'5L<V5S='EL M92!S>7-T96T@=&%S:R!D96-L87)A=&EO;BX*"@D)"DEN('1H:7,@97AA;7!L M92!S:6YC92!N;R!S>7-T96T@=&%S:RAS*2!A<F4@<W!E8VEF:65D('=I=&AI M;B!T:&4@"G-P96-I9GD@8FQO8VLL('1H92!C;VUP:6QE<B!A<'!L:65S('1H M92!R=6QE(&1E9FEN960@86)O=F4@=&\@"F1E=&5R;6EN92!I="=S('-H;W=C M86YC96QL960@9&ES<&QA>2!M;V1E+B *"B @(" @<W!E8VEF>0H@(" @(" @ M*&$@/3YO=70I/3(L,RD["B @(" @(" H8B ]/F]U="D],RPT*3L*(" @("!E M;F1S<&5C:69Y.PH*"@D)"DEN('1H:7,@97AA;7!L92!S:6YC92!T:&4@<WES M=&5M('1A<VL@9F]R(&]N+61E=&5C="!I<R!S<&5C:69I960@"F9O;&QO=VEN M9R!T:&4@83T^;W5T('1H96X@=&AE(&$]/F]U="!P871H(&=E=',@=&AE(&1E M9F%U;'0@86YD(&(]/F]U=" *9V5T<R!T:&4@;VXM9&5T96-T('-T>6QE(&%P M<&QI960@=&\@=&AE(&]U='!U="X@( H*(" @("!S<&5C:69Y"B @(" @(" H M82 ]/F]U="D],BPS*3L*(" @(" @("1S:&]W8V%N8V5L;&5D.PH@(" @(" @ M*&(@/3YO=70I/3,L-"D["B @(" @96YD<W!E8VEF>3L*"DEN('1H92!E>&%M M<&QE(&%B;W9E+" B;W5T(B!H87,@=&AE(&1E9F%U;'0@9&ES<&QA>2!M;V1E M(&9I<G-T('1H96X@"F9O;&QO=V5D(&)Y('1H92!S>7-T96T@=&%S:R!W:&EC M:"!A<'!L:65S('1H92!S:&]W8V%N8V5L;&5D(&1I<W!L87D@"FUO9&4@=&\@ M:70N("!)9B!N;R!C;VUM86YD(&QI;F4@;W!T:6]N<R!A<F4@9VEV96X@=&\@ M;W9E<G)I9&4@=&AE( IS:&]W8V%N8V5L;&5D(&UO9&4L('1H92!P871H(")O M=70B('=O=6QD(&)E(&=I=F5N('1H92!D969A=6QT( HB;F]S:&]W8V%N8V5L M;&5D(B!P<FEO<B!T;R!T:&4@<WES=&5M('1A<VLN(%1H:7,@=VEL;"!P<F]D M=6-E(&%N( IE<G)O<B!S:6YC92!A;B!O=71P=70@<&%T:"!C86YN;W0@:&%V M92!B;W1H(&1I<W!L87D@;6]D97,@87!P;&EE9"!T;R *:70N("!!;'-O+"!I M="!I<R!I;7!O<G1A;G0@=&\@;F]T92!T:&%T(&YE:71H97(@;V8@=&AE(&9O M<FUA="!T>7!E<R *;W9E<G)I9&4@=&AE(&]T:&5R('-O('1H92!U<V5R(&UU M<W0@96YS=7)E('1H870@9&EF9F5R96YT(&1I<W!L87D@"FUO9&5S(&%R92!N M;W0@<W!E8VEF:65D(&9O<B!T:&4@<V%M92!O=71P=70N"@H)"0I);B!B;W1H M(&]F('1H92!F;VQL;W=I;F<@97AA;7!L97,@<')O9'5C92!T:&4@<V%M92!R M97-U;'0@;V8@87!P;'EI;F<@"FYO<VAO=R!C86YC96QE9" H9&5F875L="D@ M=&\@<&%T:" B;W5T(B!A;F0@<VAO=V-A;F-E;&QE9"!T;R!O=71?8BX@( I3 M:6YC92!T:&4@<W!E8VEF:6,@<&%T:" B;W5T7V(B(&ES(&=I=F5N(&%S('1H M92!T87-K(&%R9W5M96YT(&EN( IS96-O;F0@97AA;7!L92P@:70@:7,@=&AE M(&]N;'D@;W5T<'5T(&%F9F5C=&5D(&)Y('1H92!S>7-T96T@=&%S:RX*"B @ M(" @<W!E8VEF>0H@(" @(" @*&$@/3YO=70I/3(L,RD["B @(" @(" H8B ] M/F]U="D],RPT*3L*(" @(" @("1S:&]W8V%N8V5L;&5D.PH@(" @(" @*&$@ M/3YO=71?8BD]-"PU*3L*(" @(" @("AB(#T^;W5T7V(I/34L-BD["B @(" @ M96YD<W!E8VEF>3L*"B @(" @<W!E8VEF>0H@(" @(" @)'-H;W=C86YC96QL M960H;W5T7V(I.PH@(" @(" @*&$@/3YO=70I/3(L,RD["B @(" @(" H8B ] M/F]U="D],RPT*3L*(" @(" @("AA(#T^;W5T7V(I/3,L-"D["B @(" @(" H M8B ]/F]U=%]B*3TU+#8I.PH@(" @(&5N9'-P96-I9GD["@I0=6QS92 G92<@ M9FEL=&5R:6YG('-T>6QE(&5X86UP;&5S"@I4:&4@9F]L;&]W:6YG(&5X86UP M;&5S(&1E<V-R:6)E('1H92!V87)I;W5S('5S97,@;V8@=&AE('!U;'-E<W1Y M;&4@"G-Y<W1E;2!T87-K('1O(&-O;G1R;VP@=&AE(&)E:&%V:6]R(&]F(")A M;&PB(&]R(")S<&5C:69I8R(@<&%T:',@;V8@=&AE( IS<&5C:69Y(&)L;V-K M+B @4VEN8V4@=&AE(&1E9F%U;'0@<G5L92!I<R!A=71O;6%T:6-A;&QY(&%P M<&QI960@=&\@86QL( IP871H<R!I;B!T:&4@86)S96YC92!O9B!A('-Y<W1E M;2!T87-K+"!N;R B9&5F875L="(@<WES=&5M('1A<VL@:7,@"G)E<75I<F5D M+B @4&%T:',@=&AA="!A<F4@=&\@=7-E('1H92!D969A=6QT("AO;BUE=F5N M="D@;F5E9"!T;R!B92 *<&QA8V5D('!R:6]R('1O(&%N>2!P=6QS97-T>6QE M('-Y<W1E;2!T87-K(&1E8VQA<F%T:6]N+@H*26X@=&AI<R!E>&%M<&QE('-I M;F-E(&YO('-Y<W1E;2!T87-K*',I(&%R92!S<&5C:69I960@=VET:&EN('1H M92 *<W!E8VEF>2!B;&]C:RP@=&AE(&-O;7!I;&5R(&%P<&QI97,@=&AE(')U M;&4@9&5F:6YE9"!A8F]V92!T;R *9&5T97)M:6YE(&ET)W,@<'5L<V4@<W1Y M;&4N( H*(" @("!S<&5C:69Y"B @(" @(" H82 ]/F]U="D],BPS*3L*(" @ M(" @("AB(#T^;W5T*3TS+#0I.PH@(" @(&5N9'-P96-I9GD["@H*"0D*26X@ M=&AI<R!E>&%M<&QE('-I;F-E('1H92!S>7-T96T@=&%S:R!F;W(@;VXM9&5T M96-T(&ES('-P96-I9FEE9" *9F]L;&]W:6YG('1H92!A/3YO=70@=&AE;B!T M:&4@83T^;W5T('!A=&@@9V5T<R!T:&4@9&5F875L="!A;F0@8CT^;W5T( IG M971S('1H92!O;BUD971E8W0@<W1Y;&4@87!P;&EE9"!T;R!T:&4@;W5T<'5T M+B @"@H@(" @('-P96-I9GD*(" @(" @("AA(#T^;W5T*3TR+#,I.PH@(" @ M(" @)'!U;'-E<W1Y;&5?;VYD971E8W0["B @(" @(" H8B ]/F]U="D],RPT M*3L*(" @("!E;F1S<&5C:69Y.PH*26X@=&AE(&5X86UP;&4@86)O=F4L(")O M=70B(&AA<R!T:&4@9&5F875L="!P=6QS92!S='EL92!F:7)S="!T:&5N( IF M;VQL;W=E9"!B>2!T:&4@<WES=&5M('1A<VL@=VAI8V@@87!P;&EE<R!T:&4@ M;VXM9&5T96-T('-T>6QE('1O(&ET+B @"DEF(&YO(&-O;6UA;F0@;&EN92!O M<'1I;VYS(&%R92!G:79E;B!T;R!O=F5R<FED92!A;&P@<'5L<V4@<W1Y;&5S M+" *=&AE('!A=&@@(F]U="(@=V]U;&0@8F4@9VEV96X@=&AE(&1E9F%U;'0@ M<W1Y;&4@(F]N+65V96YT(B!P<FEO<B!T;R *=&AE('-Y<W1E;2!T87-K+B!4 M:&ES('=I;&P@<')O9'5C92!A;B!E<G)O<B!S:6YC92!A;B!O=71P=70@<&%T M:" *8V%N;F]T(&AA=F4@8F]T:"!S='EL97,@87!P;&EE9"!T;R!I="X@($%L M<V\L(&ET(&ES(&EM<&]R=&%N="!T;R!N;W1E( IT:&%T(&YE:71H97(@;V8@ M=&AE(&9O<FUA="!T>7!E<R!O=F5R<FED92!T:&4@;W1H97(@<V\@=&AE('5S M97(@;75S=" *96YS=7)E('1H870@9&EF9F5R96YT('-T>6QE<R!A<F4@;F]T M('-P96-I9FEE9"!F;W(@=&AE('-A;64@;W5T<'5T+@H*"0D*26X@8F]T:"!O M9B!T:&4@9F]L;&]W:6YG(&5X86UP;&5S('!R;V1U8V4@=&AE('-A;64@<F5S M=6QT(&]F(&%P<&QY:6YG( IO;BUE=F5N=" H9&5F875L="D@=&\@<&%T:" B M;W5T(B!A;F0@;VXM9&5T96-T('1O(&]U=%]B+B @4VEN8V4@=&AE( IS<&5C M:69I8R!P871H(")O=71?8B(@:7,@9VEV96X@87,@=&AE('1A<VL@87)G=6UE M;G0@:6X@<V5C;VYD( IE>&%M<&QE+"!I="!I<R!T:&4@;VYL>2!O=71P=70@ M869F96-T960@8GD@=&AE('-Y<W1E;2!T87-K+@H*(" @("!S<&5C:69Y"B @ M(" @(" H82 ]/F]U="D],BPS*3L*(" @(" @("AB(#T^;W5T*3TS+#0I.PH@ M(" @(" @)'!U;'-E<W1Y;&5?;VYD971E8W0["B @(" @(" H82 ]/F]U=%]B M*3TT+#4I.PH@(" @(" @*&(@/3YO=71?8BD]-2PV*3L*(" @("!E;F1S<&5C M:69Y.PH*(" @("!S<&5C:69Y"B @(" @(" D<'5L<V5S='EL95]O;F1E=&5C M="AO=71?8BD["B @(" @(" H82 ]/F]U="D],BPS*3L*(" @(" @("AB(#T^ M;W5T*3TS+#0I.PH@(" @(" @*&$@/3YO=71?8BD],RPT*3L*(" @(" @("AB M(#T^;W5T7V(I/34L-BD["B @(" @96YD<W!E8VEF>3L*"@I03$DO5E!)($E. M5$521D%#10H)"E)O=71I;F5S('-H;W5L9"!B92!P<F]V:61E9"!B>2!T:&4@ M=F5N9&]R('1O(&%L;&]W('1H92!U<V5R('1O(&UO9&EF>2 *=&AE<V4@:6YT M97)N86P@=F%L=65S('=I=&@@96ET:&5R(%!,22!O<B!T:&4@;F5W(%9022!I M;G1E<F9A8V4N"@D*($5604Q5051)3TX@3U)$15(@4%)%0T5$14Y#10H*4VEN M8V4@:70@:7,@9&5S:7)A8FQE(&9O<B!T:&4@<VEM=6QA=&]R('1O(&)E(&9A M<W0@9'5R:6YG(&1E=F5L;W!M96YT( IA;F0@9&5B=6<@=VAI;&4@;V9F97)I M;F<@86-C=7)A=&4@<VEM=6QA=&EO;B!F;W(@=&AE(&9I;F%L('-U8FUI<W-I M;VX@"G1O('1H92!!<VEC(%9E;F1O<BP@:70@:7,@:6UP;W)T86YT('1O(&5S M=&%B;&ES:"!T:&4@;W)D97(@;V8@"G!R96-E9&5N8V4@=&AE(&-O;7!I;&5R M(&UU<W0@9F]L;&]W+B @5&AE(&1E9F%U;'1S(&EN(&YE:71H97(@=&AE( IC M;VUM86YD(&QI;F4@;W(@<WES=&5M('1A<VMS(&%R92!S=7!P;&EE9"!A<F4@ M=&AE(&-U<G)E;G0@5F5R:6QO9UA,( ID969A=6QT('9A;'5E<R!F;W(@8F]T M:"!O<'1I;VYS+B @5&AE($%324,@5F5N9&]R(&YE961S('1O(&5I=&AE<B * M<W5P<&QY('1H92!A<'!R;W!R:6%T92!S>7-T96T@=&%S:W,@=VET:&EN('1H M92!S<&5C:69Y(&)L;V-K(&]R(&1E9FEN92 *=&AE(&%P<')O<')I871E(&-O M;6UA;F0@;&EN92!O<'1I;VYS(')E<75I<F5D(&9O<B!F:6YA;"!S:6UU;&%T M:6]N( IS=6)M:7-S:6]N+B @5&AE(&9O;&QO=VEN9R!S=6UM87)I>F5S('1H M92!P<F5C961E;F-E('=H:6-H(&UU<W0@8F4@"F9O;&QO=V5D.@H*"3%S="D@ M5&AE(&-O;6UA;F0@;&EN92!O<'1I;VYS+@H*"3)N9"D@5&AE('-Y<W1E;2!T M87-K<RX*"@DS<F0I(%9E<FEL;V<@4VEM=6QA=&]R($1E9F%U;'1S+@H*268@ M=&AE(%9E<FEL;V<@8V]M;6%N9"!@<F5S971A;&P@:7,@9VEV96X@=&AE('-I M;75L871O<B!W:6QL('5S92 *=&AI<R!O<F1E<B!T;R!D971E<FUI;F4@:70G M<R!N97<@9&5F875L=',*"@I41B!!;F%L>7-I<R F(%)A=&EO;F%L90HM+2TM M+2TM+2TM+2TM+2TM+2TM+2TM+2T*06UM96YD($E%144@,3,V-"!,4DT@87,@ M<')O<&]S960@8GD@875T:&]R(&)E8V%U<V4@=&AI<R!N97<@9F5A='5R90II M<R!N96-E<W-A<GD@9F]R(&%D9&ET:6]N('1O('1H92!L86YG=6%G90H*"E93 M1RU41B!296-O;6UE;F1A=&EO;B!F;W(@8W5R<F5N="!)145%(%-T9" *+2TM M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+0H\375S M="!B92!F:6QL960@8GD@875T:&]R(&]F($%N86QY<VES/@H*"E931RU41B!2 M96-O;6UE;F1A=&EO;B!F;W(@1G5T=7)E(%)E=FES:6]N<R!O9B!3=&0*+2TM M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM M+2T*/$-O=6QD(&)E(&9I;&QE9"!B>2!A=71H;W(@;V8@06YA;'ES:7,^"@H* !"BT* end ---------- X-Sun-Data-Type: default X-Sun-Data-Description: default X-Sun-Data-Name: fullskew_ir.txt
IEEE 1364 VSG Issue Number: ATF004
Classification: Timing
IEEE 1364 Version: IEEE 1364'98
Summary: The $skew timing check in Verilog checks that the data event occurs (if it occurs at all) within the constraint limit after the reference event. It doesn't perform a check where either of the two signals could occur first. $fullskew addresses this need, as well as addresses problems related to the time of the violation report and the ambiguity of the meaning of transitions that take place while the corresponding condition is false.
Related Issues: None <Xref all related issues by number.>
Relevant LRM Sections: section 14
Key Words and Phrases: TBD <IEEE 1364 terms>
Priority - Submitted: Critical
<One of the following:> Critical Important Desirable
Priority Task Force 1 <TF assigns.>
<One of the following:> 1 2 3 4 Unknown <Author assigns.>
Current Status: TF-Approved
Submitted <Author assigns.> Analyzed <TF assigns.> TF-Approved <TF assigns.> VSG-Approved <TF assigns.> Superceded <TF assigns.>
Superseded By: N/A
IEEE Ballot Disposition: TBD
<One of the following:> Unknown Closed (All Issues Completely Addressed) Bugs Fixed, Enhancements Outstanding (No TF Issues) Superseded (TF Issues Outstanding)
Disposition Rationale: TBD<To be completed by the TF>
Superseded By: N/A <superceding issue's number>
Date Submitted: 22 July 1997 Author of Submission: Prabhu Krishnamurthy Author's Affiliation: LSI Logic Corporation Author's Post Address: 1501 McCarthy Blvd, Milpitas CA 95035 Author's Phone Number: (408)433-6118 Author's Fax Number: (408)433-4156 Author's Net Address: prabhu@lsil.com
----------------------- Date Analyzed: 12 August 1997 Author of Analysis: Prabhu Krishnamurthy Revision Number: $Revision: 1.1 $ Date Last Revised: $Date: 1997/08/12 $
Description of Problem ---------------------- Following section describes the issues with the way the $skew check works right now.
Example: $skew(posedge CP &&& CPN, negedge CPN, 2, notifier)
1. In the above case, the skew check is initiated when the positive edge on CP occurs when CPN is "1". This is marked as the reference event. If the negative edge on CPN happens at, say, 10ns after the reference event, the violation gets reported at that time and the notifier is toggled. The issue here is as follows:
i. Since skew time is a "max" timing constraint, the violation should be reported as soon as the "limit" elapses. This way, the violation reporting, notifier toggling and the action following that are not delayed.
ii. Another issue with the current behavior is that the triggering event is active even after the conditioning signal becomes FALSE, thereby reporting violations for all subsequent changes to the data event. This is due to the fact that the triggering event should happen again (satisfying the CONDITION on the reference event) to begin another check. ___ ___ ___ ___ ___ CP ___| |___| |___| |___| |___| |__ ^ _________ ___ ___ ___ ___ CPN |___| |___| |___| |___| 1 2 3 4 The first edge on CP (marked with ^) triggers the first skew check and reports a violation when CPN event 1 happens (because the skew exceeded the limit). The trigger still remains active as the CONDITION on the reference is never again true when CP experiences a posedge. This causes skew violations to be reported for events 2,3,4... on the CPN signal. 2. In cases where the posedge of CP happens first followed by more transitions on CP without any change to the CPN signal, the skew violation does not get reported until negedge of CPN happens. This will be resolved with the timer based approach. 3. Since $skew check in Verilog is "uni-directional" ie. the first signal is the reference event (which should happen first to initiate a check) and the second signal is a data event (which is when the check is actually performed), another $skew statement is required to cover the bi-directional nature of most skew checks. Following is the bi-directional counterpart for the above skew check for the same edges of the reference and data signals but in the reverse order.
ie. $skew(negedge CPN &&& ~CP, posedge CP, 2 , notifier)
Proposed Resolution -------------------
The new timing $fullskew check that is being proposed is to overcome the above limitations of the existing $skew timing check.
Syntax Description ------------------
$fullskew(ref_event1, ref_event2, limit1, limit2, notifier, evr_flag, dormant_flag)
<Notifier is alwyas last in other timing checks - perhpas it should be last here, too>
ref_event1 - edge-triggered event which can accept an edge modifier and a condition
ref_event2 - edge-triggered event which can accept an edge modifier and a condition
limit1 - Positive constant expression or specparam specifying the maximum by which ref_event1 can precede ref_event2.
limit2 - Positive constant expression or specparam specifying the maximum by which ref_event2 can precede ref_event1.
The limits are not optional. notifier (optional) - Register
evr_flag (optional) - Early Violation Report flag. Should be either null or a constant. A null or zero value indicates that consecutive edges of one signal with no edges on the other should not be reported as a violation. If a transition on one signal occurs late with respect to the other it is reported as a violation at that time. This is similar to the way $skew works today.
A non-zero value indicates that a late transition is reported immediately after the constraint period expires. In this case, transitions are required to occur - a missing transition on one of the signals is always reported as a violation.
dormant_flag (optional) - Should be either null or a constant. A null or zero value indicates that when this constraint is already active it will remain active after subsequent transitions on the same signal which caused it to be active when those transitions take place while the condition is false.
A non-zero value indicates that under these same circumstances the check will become dormant.
Details ------- When no edge is specified on either reference signal, then any edge on either signal can be the trigger that initiates a constraint period waiting for the transition on the other signal. A constraint period that ends with a violation begins another constraint period, while one that ends with no violation does not begin another constraint period.
$fullskew behavior is illustrated in this example, which specifies that matching edges are required and that the violations be reported immediately after the end of the constraint period.
$fullskew(posedge REF, posedge DAT, 5, 5, ntfr, 1);
Assume that beginning at simulation startup the REF and DAT signals transition in this manner, and that the transitions, when they occur, obey the constraints: ___ ___ ___ ___ ___ ___ (a) REF xxxx___| |___| |___| |___| |___| |___| |_ ___ ___ ___ ___ ___ DAT xxxxxxxxxxx___| |___| |___| |___| |___| |__
When the first posedge on REF takes place DAT is still in the X state, and the constraint period elapses with no posedge on DAT, so a timing violation message is issued. The next signal to experience a posedge, be it REF or DAT, begins the next constraint period. In the example it is DAT that transitions next with a posedge, and since REF occurs within the 5 unit constraint period there is no violation. This posedge on REF dos not begin anotehr constraint period, since it is already ending one that does not result in a violation. The next posedge transition of DAT begins another constraint period, and so forth.
This next situation is similar to (a), differing only in that transitions on REF begin the constraint period after the initial cycle while DAT is still initializing:
___ ___ ___ ___ ___ ___ (b) REF xxxx___| |___| |___| |___| |___| |___| |__ ___ ___ ___ ___ ___ DAT xxxxxxxxxxxxx___| |___| |___| |___| |___| |_
Setting the evr_flag to zero or null specifies behavior analogous to $skew where the other edge is not required to occur:
$fullskew(posedge REF, posedge DAT, 5, 5, ntfr, 0);
The waveforms in (a) would not generate a timing violation message until the first transition of DAT. This edge of DAT would then be used to begin a new constraint period, sinc eit ended a constraint period that resulted in a violation.
The waveforms in (b) would not generate any timing violation message at all.
One interesting aspect of $fullskew behavior is that when the timing is truly off between the two signals there will be two violations given per cycle. The first edge of one signal will occur, and when the edge on the other signal is late a timing violation message is issued and a new constraint period is begun. The next edge of the original signal is now late relative to the other signals edge, and another violation is issued.
How conditions affect timestamp events is an important issue, and is the motivating factor for the dormant flag. Take this $skew check:
$skew(posedge CLK1 &&& CND, CLK2, 50);
Presume that CLK1 experiences transitions 0=>1 at time 100 while CND is true, then CND becomes false at time 110, followed by CLK1 transitioning low at time 150 and high at time 200. If CLK2 now transitions at time 220 $skew will issue a violation against the last CLK1 transition while CND was true, which was at time 100. By this measure CLK2 is late, arriving after 120 time units instead of the required 50. In some designs this might not make sense because they intend that a CLK1 transition with a false condition makes the check dormant (ie, it is no longer looking for a matching signal). This is the justification for the dormant flag of the $fullskew check.
PLI/VPI INTERFACE TBD TF Analysis & Rationale ------------------------ Ammend IEEE 1364 LRM as proposed by author because this new feature is necessary for addition to the language
VSG-TF Recommendation for current IEEE Std ------------------------------------------- <Must be filled by author of Analysis>
VSG-TF Recommendation for Future Revisions of Std -------------------------------------------------- <Could be filled by author of Analysis>
---------- X-Sun-Data-Type: default X-Sun-Data-Description: default X-Sun-Data-Name: recrem_ir.txt
IEEE 1364 VSG Issue Number: ATF???
Classification: Timing
IEEE 1364 Version: IEEE 1364'98
Summary:
Checking for setup and hold constraints is provided in Verilog HDL by the $setup, $hold and $setuphold constructs. The same suite of checks is missing for recovery times, where only $recovery exists. $recrem, along with $recovery and $removal (also new), fills out the suite of recovery checks.
Related Issues: $recovery, $removal (ATF???)
Relevant LRM Sections: 14
Key Words and Phrases: timing checks
Priority - Submitted: Critical
<One of the following:> Critical Important Desirable
Priority Task Force 1 <TF assigns.>
<One of the following:> 1 2 3 4 Unknown <Author assigns.>
Current Status: TF-Approved
Submitted <Author assigns.> Analyzed <TF assigns.> TF-Approved <TF assigns.> VSG-Approved <TF assigns.> Superceded <TF assigns.>
Superseded By: N/A
IEEE Ballot Disposition: Enhancement
<One of the following:> Unknown Closed (All Issues Completely Addressed) Bugs Fixed, Enhancements Outstanding (No TF Issues) Superseded (TF Issues Outstanding)
Disposition Rationale: TBD<To be completed by the TF>
Superseded By: N/A <superceding issue's number>
Date Submitted: 30 July 1997 Author of Submission: Ted Elkind Author's Affiliation: Cadence Design Systems Author's Post Address: 270 Billerica Road, Chelmsford, MA 01824 Author's Phone Number: (508) 262-6354 Author's Fax Number: (508) 262-6636 Author's Net Address: elkind@cadence.com
----------------------- Date Analyzed: 12 August 1997 Author of Analysis: Ted Elkind Revision Number: $Revision: 1.0 $ Date Last Revised: $Date: 1997/08/13 $
Description of Problem ----------------------
Summary -------
$recovery specifies a recovery period that begins at the control signal edge and extends for a given period of time after, during which the clock signal is not permitted to transition. There is no complementary check that defines a period before the control signal edge and extending up to that edge during which the clock signal is not permitted to transition. $recrem allows definition of both the recovery and removal limits in a single check.
Detail ------
As long as the recovery limit is positive the control signal edge can always serve as the starting point for the recovery period, that period during which the clock signal cannot transition without rendering device behavior ambiguous. But this is arbitrary, and it is more accurate to allow exlicit definition of the beginning of the recovery period. Also, because of internal device delays, the recovery limit is not always positive, and when this is the case then the control signal edge can no longer serve as the starting point for the recovery period, since it has not yet occurred.
$recrem permits specification of both the recovery and removal limits. Removal is the time period before the control signal edge, and recovery is the time period after. The sum of these two limits must be greater than or equal to 0, else a negative violation region is defined.
When the removal limit is negative it means that the control signal edge has already taken place before the constraint period has begun.
Usage Model -----------
$recrem(reference_event, data_event, limit, notifier, timestand_condition, timecheck_condition, delayed_reference, delayed_data)
reference event - edge-triggered event, usually corresponds to control signals like clear, reset, set.
data_event - Upper bound event, usually corresponds to clock signals
limit - Positive constant expression or specparam
notifier (optional) - Register
timestamp_condition - Signal conditioning the timing check
timecheck_condition - Signal conditioning the timing check
delayed_reference - Delayed control signal for internal connection to model
delayed_data - Delayed clock signal for internal connection to model
PLI/VPI INTERFACE TBD TF Analysis & Rationale ------------------------ Ammend IEEE 1364 LRM as proposed by author because this new feature is necessary for addition to the language
VSG-TF Recommendation for current IEEE Std ------------------------------------------- <Must be filled by author of Analysis>
VSG-TF Recommendation for Future Revisions of Std -------------------------------------------------- <Could be filled by author of Analysis>
---------- X-Sun-Data-Type: default X-Sun-Data-Description: default X-Sun-Data-Name: removal_ir.txt
IEEE 1364 VSG Issue Number: ATF???
Classification: Timing
IEEE 1364 Version: IEEE 1364'98
Summary:
Checking for setup and hold constraints is provided in Verilog HDL by the $setup, $hold and $setuphold constructs. The same suite of checks is missing for recovery times, where only $recovery exists. $removal, along with $recovery and $recrem (also new), fills out the suite of recovery checks.
Related Issues: $recovery, $recrem (ATF???)
Relevant LRM Sections: 14
Key Words and Phrases: timing checks
Priority - Submitted: Critical
<One of the following:> Critical Important Desirable
Priority Task Force 1 <TF assigns.>
<One of the following:> 1 2 3 4 Unknown <Author assigns.>
Current Status: TF-Approved
Submitted <Author assigns.> Analyzed <TF assigns.> TF-Approved <TF assigns.> VSG-Approved <TF assigns.> Superceded <TF assigns.>
Superseded By: N/A
IEEE Ballot Disposition: Enhancement
<One of the following:> Unknown Closed (All Issues Completely Addressed) Bugs Fixed, Enhancements Outstanding (No TF Issues) Superseded (TF Issues Outstanding)
Disposition Rationale: TBD<To be completed by the TF>
Superseded By: N/A <superceding issue's number>
Date Submitted: 30 July 1997 Author of Submission: Ted Elkind Author's Affiliation: Cadence Design Systems Author's Post Address: 270 Billerica Road, Chelmsford, MA 01824 Author's Phone Number: (508) 262-6354 Author's Fax Number: (508) 262-6636 Author's Net Address: elkind@cadence.com
----------------------- Date Analyzed: 12 August 1997 Author of Analysis: Ted Elkind Revision Number: $Revision: 1.0 $ Date Last Revised: $Date: 1997/08/13 $
Summary -------
$recovery specifies a recovery period that begins at the control signal edge and extends for a given period of time, during which the clock signal is not permitted to transition. There is no complementary check that defines a period before the control signal edge and extending up to that edge during which the clock signal is not permitted to transition. $removal fills the need for the complementary check for $recovery.
Details -------
As long as the recovery limit is positive the control signal edge can always serve as the starting point for the recovery period, that period during which the clock signal cannot transition without rendering device behavior ambiguous. But this is arbitrary, and it is more accurate to allow explicit definition of the beginning of the recovery period. Also, because of internal device delays, the recovery limit is not always positive, and when this is the case then the control signal edge can no longer serve as the starting point for the recovery period, since it has not yet occurred.
A new limit, removal, is introduced. It represents the part of the recovery period before the control signal edge during which the clock edge is not permitted to occur. The removal limit must not be negative.
Usage Model -----------
$removal(reference_event, data_event, limit, notifier)
reference event - edge-triggered event, usually corresponds to control signals like clear, reset, set.
data_event - Upper bound event, usually corresponds to clock signals
limit - Positive constant expression or specparam
notifier (optional) - Register
PLI/VPI INTERFACE TBD TF Analysis & Rationale ------------------------ <Must be filled by author of Analysis>
VSG-TF Recommendation for current IEEE Std ------------------------------------------- <Must be filled by author of Analysis>
VSG-TF Recommendation for Future Revisions of Std -------------------------------------------------- <Could be filled by author of Analysis>
---------- X-Sun-Data-Type: default X-Sun-Data-Description: default X-Sun-Data-Name: ntc_ir.txt
IEEE 1364 VSG Issue Number: <To be assigned by the TAG.> Classification: Timing IEEE 1364 Version: IEEE 1364'98 Summary: Extend the capability of the $setuphold timing check to accomodate negative limits, as required to model situations where there is large time skew between data and clock paths from the cell boundary to the internal storage node whose physical effects are to be modeled. The feature to be achieved by deriving internal delayed versions of timingcheck signals, which can be made available by the user for the purpose of timing of functional behavior. The method for deriving delays for timingcheck signals to be unambiguously described, and the resulting delay values must be unique. signals, Related Issues: $recrem (no. ?) Relevant LRM Sections: 14.5 Key Words and Phrases: Negative Timing Check, NTC +neg_tchk timestamp condition timecheck condition reference, delayed reference data, delayed data negative timingcheck adjustment Priority - Submitted: Important Priority - Task Force 1 Current Status: Submitted Superseded By: N/A IEEE Ballot Disposition:<One of the following:> Unknown Closed (All Issues Completely Addressed) Bugs Fixed, Enhancements Outstanding (No TF Issues) Superseded (TF Issues Outstanding) Disposition Rationale: <To be completed by the TF> Superseded By: <superceding issue's number> ----------------------- Date Submitted: 21 07 1997 Author of Submission: Paul Colwill Author's Affiliation: Viewlogic Systems, Inc. Author's Post Address: 20230 Steven's Creek Blvd., Suite C Cupertino, CA95014 Author's Phone Number: (408) 863-3637 Author's Fax Number: (408) 873-0157 Author's Net Address: pcolwill@viewlogic.com ----------------------- Date Analyzed: TBD <Enter date analyzed in dd month year form.> Author of Analysis: TBD <Enter author of analysis.> Revision Number: $Revision: 0.1 Date Last Revised: $Date: 1997/xx/xx xx:xx
Description of Problem ---------------------- Negative Timing Checks ======================
1. The need for negative value timing checks 2. Requirements for accurate simulation 3. Implicit Delays on Signals 4. Extended Timing Check Syntax 5. Delay Calculation 6. Conditions 7. Notifier 8. User switch 9. SDF
1. The need for negative value timing checks: -----------------------------------------
Setup and hold timing checks define a timing violation window around the reference signal in which the data should remain constant. Any change of the data during the specified window causes a timing violation. VCS will report the timing violation and allow the user (through the notifier register) to cause other actions to take place in the model. e.g The model could force the output of a flip-flop to "X" when it detects a timing violation.
A positive value on both $setup and $hold implies that this violation window straddles the reference signal, which is usually true for the point in the physical cell circuitry where the reference and data feed the actual sequential element.
___________________ clock ________________/ _____________ data XXXXXXXXXX_____________XXXXXXXXXXXXX
>------| ........... Setup Time (+) |------< ........... Hold Time (+)
Figure 1 - Data constraint interval, positive setup/hold
Analog simulators are often used to measure the stability window at the cell boundary. In ASIC cells, there can be situations when there is a considerable difference in the delay paths between the data and reference signals from the outer physical boundary of the cell to the sequential element in the interior of the cell. If the timing relationships between the data and reference signals are defined at the cell boundaries (as opposed to at the internal sequential element), we may have a violation window fully before or fully after the reference signal. If the violation window is entirely before the reference signal then we specify the hold time with a negative value. If the violation window is entirely after the reference signal then specify the setup time with a negative value.
ASIC Cell +---------------------------+ | +------+ | | +----+ | | | data--------------| D1 |----|Seq. |-----------output | +----+ | | | | |Elem. | | | +----+ | | | clk---------------| D2 |----| | | | +----+ | | | | +------+ | +---------------------------+
Negative Hold time (D1 > D2) ----------------------------
_______________________________ clock ______/ _____________ data XXXXXXXXXX_____________XXXXXXXXXXXXX
|--> ........... Setup Time (-) |----------------< ........... Hold Time (+)
Negative Setup time (D2 > D1) ---------------------------- ___________ clock __________________________/ _____________ data XXXXXXXXXX_____________XXXXXXXXXXXXX
>----------------| ........... Setup Time (+) <--| ........... Hold Time (-)
Very fast sequential circuits (such as deep sub-micron designs) will quite often have either negative setup times or negative hold times. If an ASIC vendor chooses to set these negative values to zero, then they will be underestimating the actual speed of their ASIC's. However, if they decide to use the negative values, then the digital simulator and the ASIC cell models must have special capabilities to produce accurate, working models.
2. Requirements for accurate simulation: ------------------------------------ In order to accurately model negative value timing checks:
1) If the signal changes in the violation window then a timing violation should be triggered.
2) the value of the data that is latched must be the one that is stable during the violation window.
To facilitate these modeling requirements VCS creates delayed copies of the data and reference signals that appear in the timing checks. VCS creates these delayed signals such that the violation window always overlaps the reference signal for the DELAYED signals. VCS will also accommodate setup and hold values that become negative (or positive) during the back annotation process (e.g. $sdf_annotate).
The ASIC vendor can then create a cell model that uses these delayed signals. This model will be much simpler than if the ASIC vendor had attempted to accomodate negative value timing checks without the use of this feature.
The next section describes how these delayed signals are created.
3. Implicit Delays on Signals: --------------------------
Negative timing checks implicitly define relative delays between the signals in the timing check. e.g.
T1: $setuphold(CLK,DATA,-10,20);
T1 implies that CLK is delayed by at least 10 time units with respect to DATA. T1 also implies that CLK is not delayed by more than 20 time units with respect to data.
Therefore, TI defines an upper and lower bound on the relative delays between the two signals. Every other timing check also defines a similar set of bounds on the two signals in the timing check.
If the actual delays that VCS applies to the various delayed signals satisfy the above constraints on all the timing checks, then the we can be sure that conditions 1 and 2 (from Section 2 above) are satisfied.
Therefore, if a violation occurs, in the absence of (user's) notifier conditioning logic to invalidate data, the exact time that data is latched is not under the control of the user, but it will satisfy the constraints implied by the collection of timingcheck declarations for the module. We believe that this should not matter to the user because a timing violation has occurred, indicating that the data value latched cannot be relied upon as being correct.
4. Extended Timing Check Syntax: ----------------------------
VCS provides these delayed signals to the user through additional parameters and signals in the timing check system call. The syntax of the timing check becomes:
$setuphold(reference,data,setup,hold,notifier,timestamp_cond, timecheck_cond,delayed_reference,delayed_data);
In this extended $setuphold syntax, the notifier, timestamp_cond, timecheck_cond, delayed_reference, and delayed_data are optional. Delayed_reference and delayed_data are nets that are driven by the timing check. In this extended syntax, the user has the option of specifying individual conditioning signals on either/both the reference and data signals.
Note that the timestamp_cond expression in this example applies to the data (arg#2) for $setup, but is applied to the reference (arg#1) for $hold. Similarly, the timecheck_cond applies to the reference (arg#1) for $setup, and the data (arg#2) for the $hold. Also, note that timestamp_cond and timecheck_cond override any timingcheck condition that may be included in the first two arguments of the timingcheck declaration.
5. Delay Calculation: -----------------
VCS uses each timing check to define a delay relationship between the signals in the timing check. For example:
T2: $setuphold(CLK,DATA,-10,20,,,,del_CLK,del_DATA);
T2 defines a delay relationship between del_CLK and del_DATA, which says that if del_DATA is delayed by 'd' time units with respect to DATA, then del_CLK will be delayed at least 'd+10' and at most 'd+20' timeunits with respect to CLK. Any of these delay values will ensure that the timing violation window (when the data is stable) overlaps the clock.
Let
dclk : delay between CLK and del_CLK ddata: delay between DATA and del_DATA
then T2 implies
20 > dclk - ddata > 10
Thus a set of timing checks defines a set of delay relationships. Hereafter we will be representing each such relationship as (del_CLK,del_DATA,10,20).
For example:
T3: $setuphold(posedge CP, D, -10, 20, notifier, ,, del_CP, del_D); T4: $setuphold(posedge CP, TI, 20, -10, notifier, ,, del_CP, del_TI); T5: $setuphold(posedge CP, TE, -4, 8, notifier, ,, del_CP, del_TE);
T3, T4 and T5 define the following set of relationships respectively:
(dCP, dD, 10, 20), (dTI, dCP, 10, 20), (dCP, dTE, 4, 8).
VCS satisfies all of these relationships and produces the following delays:
dCP -- 11 dD -- 0 dTI -- 22 dTE -- 6
Sometimes the delays implied by the timing checks may be mutually inconsistent. In that case, VCS will change the smallest negative delay to 0 and change the timing check to reflect that. For example:
T6: $setuphold(I1,CLK,-5,15,,,,I1_del,CLK_del); T7: $setuphold(I1,CLK,10,-6,,,,I1_del,CLK_del);
T6 implies (I1,CLK,5,15) and T7 implies (CLK,I1,6,10).
In this case the new timing checks would be:
T6': $setuphold(I1,CLK, 0,10,,,,I1_del,CLK_del); T7: $setuphold(I1,CLK,10,-6,,,,I1_del,CLK_del);
and the delays are dI1 = 6 and dCLK = 0.
The use of inequalities (as opposed to equalities) as constraints on the delays gives the simulator more freedom in choosing the actual delays. This in turn allows the simulator to create a consistent set of accurate delays in more cases than if equalities had been used.
The following example proves this point. (This example is from VITAL IR:230).
Ta : $setuphold(MC, D,0.41, 0.10,,,,del_MC, del_D); Tb : $setuphold(SLC,MC,0.60,-0.30,,,,del_SLC,del_MC); Tc : $setuphold(SLC, D,0.53,-0.18,,,,del_SLC,del_D);
If the delays implied in these timing checks are modeled with equalities then the following equations are derived:
Ea: dMC - dD = 0; Eb: dMC - dSLC = 0.30; Ec: dD - dSLC = 0.18;
As can be seen these equations have no solution. The simulator will have to make the smallest negative delay zero and ignore the associated timing check when creating the delayed signals. This in turn will cause the ASIC to appear to be slower than it actually is.
On the other hand if the delay constraints are modelled as inequalities then we have:
Ia: 0.41 > dMC - dD > - 0.10 Ib: 0.60 > dMC - dSLC > 0.30 Ic: 0.53 > dD - dSLC > 0.18
And these inequalities do have a solution:
dSLC = 0.0; dD = 0.22; dMC = 0.31;
To recap the delay calculation procedure, VCS uses the timing checks to create a set of inequalities for signal delays. It then tries to find delay values which satisfy these inequalities. If no such solution is found, the smallest negative delay is set to zero and the associated timing check is no longer used in the delay calculation.
6. Conditions: ----------
Take the following example:
assign TE_cond_D = (dTE !== 1'b1); assign TE_cond_TI = (dTE !== 1'b0); assign DXTI_cond = (dTI !== dD);
specify $setuphold(posedge CP, D, -10, 20, notifier, ,TE_cond_D, dCP, dD); $setuphold(posedge CP, TI, 20, -10, notifier, ,TE_cond_TI, dCP, dTI); $setuphold(posedge CP, TE, -4, 8, notifier, ,DXTI_cond, dCP, dTE); endspecify These timing checks define the following violation windows (The violation windows are marked in ===) :
_________________________________ CP _______________________/ 500
D XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX==========XXXXXXXXXXXXXXX 510 520
TE XXXXXXXXXXXXXXXXXXXXXXXXXX====XXXXXXXXXXXXXXXXXXXXXXXXXXX 504 508
TI XXXXXXX==========XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 480 490
The delays calculated are:
dCP -- 11 dD -- 0 dTI -- 22 dTE -- 6
There are two places where the conditioning signals could possibly be checked.
1. Conditioning signals could be checked when the delayed signals (in this case dCP,dD etc.) change.
... or ...
2. Conditioning signals could be checked when the non-delayed signals (in this case CP,D etc.) change.
If the conditioning signals don't change during the delay time, then both options will yield the same result. However, if the conditioning signals change during the delay time, the results may differ. Which approach is correct (or more suitable) depends on how the conditioning signals are calculated.
If the conditioning signals are calculated by using delayed signals (as is shown in this case) then approach 1 is better. This also seems to be closer to the physical reality as the user is usually interested in relationships between delayed signals. Since the data is latched into the sequential circuit through the use of the delayed signals, it is logical that the conditions at the time of the latching are of most interest.
In the above example the user is really interested in finding the equality between dTI and dD and not TI and D since dD and dTI are the signals that drive the latching.
If the conditioning signals are calculated using the undelayed signals then approach 2 is better. This implies that the conditions are being checked at the boundary of the cell so they should be used to condition the signals at the boundary.
VCS will default to case 1 but will have a compile time switch to change to case 2. The ASIC vendor can also use the non-extended syntax of the $setuphold timing check to check the timing of the non-delayed signals at the cell boundary. The switch to change to case 2 will be +NTC2.
7. Notifier --------
There are same two choices for when to toggle the notifier. The notifier can either be toggled when the timing check would have been triggered at the boundary or it can be toggled when the timing check is triggered with respect to the delayed signals. VCS will toggle the timing check notifier when it is triggered with respect to the delayed signals. The reason for this choice is that if the notifier is toggled at the boundary then the flip-flop will be driven to x (which is the normal use of the notifier) before the data signals reach the physical device. The flip flop will then subsequently be clocked by the the delayed signals, defeating the use of the notifier register.
An example illustrates this point.
module top; reg d,clk,reset; DFF d1(d,reset,clk,q); initial $monitor($time,"d = %b clk = %b q = %b",d,clk,q);
initial begin reset = 0; clk = 0; d = 0; #20 clk = 1; #7 d = 1; end
endmodule module DFF(D,RST,CLK,Q); input D,RST,CLK; output Q; reg notifier; DFF_UDP d2(Q,dCLK,dD,dRST,notifier); specify (D => Q) = 20; (CLK => Q) = 20; $setuphold(posedge CLK,D,-5,10,notifier,,,dCLK,dD); $setuphold(posedge CLK,RST,-8,12,notifier,,,dCLK,dRST); endspecify endmodule primitive DFF_UDP(q,clk,data,rst,notifier); output q; reg q; input data,clk,rst,notifier; table // clock data rst notifier state q // ------------------------------ r 0 0 ? : ? : 0 ; r 1 0 ? : ? : 1 ; f ? 0 ? : ? : - ; ? ? r ? : ? : 0 ; ? * ? ? : ? : - ; ? ? ? * : ? : x ; endtable endprimitive
This is a model of a positive edge-triggered flip-flop with reset. It goes to x on the notifier toggle.
The delays calculated according to timing checks are: dCLK 9 dD 3 dRST 0
The wave forms are:
20 ----------------------- | CLK ----------------- 27 ______________ | D ------------------------- 29 -------------- | dCLK ------------------------------- 30 ------------- | dD ---------------------------------
The violation window is from 25 to 30. If the notifier is toggled according to signals at the cell boundary then the notifier is toggled at 27, which produces an x on Q at 27 but this x never reaches the cell boundary as the value of dD (i.e. 0) is latched into the flip flop at 29. The output is:
0d = 0 clk = 0 q = x 20d = 0 clk = 1 q = x "testnot2.v", 27: Timing violation in top.d1 $setuphold( posedge CLK:20, D:27, -5, 10 ); 27d = 1 clk = 1 q = x 47d = 1 clk = 1 q = 0
So although the notifier is toggled the outside of the cell does not see an 'x' on the flip flop output.
On the other hand if the notifier is triggered according to the delayed signals then the notifier is toggled at 30 and the flip flop stays at 'x'. The output in that case is
0d = 0 clk = 0 q = x 20d = 0 clk = 1 q = x 27d = 1 clk = 1 q = x "testnot2.v", 28: Timing violation in top.d1 $setuphold( posedge CLK:20, D:27, limits: (-5,10) );
which is the correct behaviour.
8. User Switches: -------------
The user turns on negative timing checks from the command line with the plus option +neg_tchk. In the absence of this option the negative values will be changed to zero. +notimingcheck in the presence of +neg_tchk will only switch off the timing messages and notifier toggling. +no_notifier is still available in combination with +neg_tchk, all it will do is to prevent notifiers from toggling, but violation messages will still be emitted.
The delays used for the delayed signals will remain the same. The user switch to check conditioning signals at the boundary is +NTC2. (as explained in Section 6)
9. SDF ---
The user will be able to annotate any timing check of types setuphold and recovery with negative values provided these conditions are true:
a. The timing check is created with the extended syntax, i.e. with the delayed signals.
b. The model is compiled with +neg_tchk.
c. The sum of the two limits is greater than zero.
TIMINGCHECK statements in the SDF file read by VCS will cause annotation of timingchecks in the model which match the edge and condition arguments in the SDF statement, as docimented in the SDF3.0 specification. If the SDF statement has SCOND and/or CCOND expressions specified, they must match the timestamp_cond and/or timestamp_cond (respectively) in the timingcheck declaration for annotation to occur. If there is no SCOND or CCOND clauses in the SDF statement, all timingchecks that otherwise match are annotated.
Proposed Resolution ------------------- <Could be filled by author of Submission>
TF Analysis & Rationale ------------------------ <Must be filled by author of Analysis>
VSG-TF Recommendation for current IEEE Std ------------------------------------------- <Must be filled by author of Analysis>
VSG-TF Recommendation for Future Revisions of Std -------------------------------------------------- <Could be filled by author of Analysis>
_ ---------- X-Sun-Data-Type: postscript-file X-Sun-Data-Description: postscript-file X-Sun-Data-Name: vcd.ps
%!PS-Adobe-3.0 %%BoundingBox: (atend) %%Pages: (atend) %%PageOrder: (atend) %%DocumentFonts: (atend) %%Creator: Frame 4.0 %%DocumentData: Clean7Bit %%EndComments %%BeginProlog % % Frame ps_prolog 4.0, for use with Frame 4.0 products % This ps_prolog file is Copyright (c) 1986-1993 Frame Technology % Corporation. All rights reserved. This ps_prolog file may be % freely copied and distributed in conjunction with documents created % using FrameMaker, FrameBuilder and FrameViewer as long as this % copyright notice is preserved. % % Frame products normally print colors as their true color on a color printer % or as shades of gray, based on luminance, on a black-and white printer. The % following flag, if set to True, forces all non-white colors to print as pure % black. This has no effect on bitmap images. /FMPrintAllColorsAsBlack false def % % Frame products can either set their own line screens or use a printer's % default settings. Three flags below control this separately for no % separations, spot separations and process separations. If a flag % is true, then the default printer settings will not be changed. If it is % false, Frame products will use their own settings from a table based on % the printer's resolution. /FMUseDefaultNoSeparationScreen true def /FMUseDefaultSpotSeparationScreen true def /FMUseDefaultProcessSeparationScreen false def % % For any given PostScript printer resolution, Frame products have two sets of % screen angles and frequencies for printing process separations, which are % recomended by Adobe. The following variable chooses the higher frequencies % when set to true or the lower frequencies when set to false. This is only % effective if the appropriate FMUseDefault...SeparationScreen flag is false. /FMUseHighFrequencyScreens true def % % PostScript Level 2 printers contain an "Accurate Screens" feature which can % improve process separation rendering at the expense of compute time. This % flag is ignored by PostScript Level 1 printers. /FMUseAcccurateScreens true def % % The following PostScript procedure defines the spot function that Frame % products will use for process separations. You may un-comment-out one of % the alternative functions below, or use your own. % % Dot function /FMSpotFunction {abs exch abs 2 copy add 1 gt {1 sub dup mul exch 1 sub dup mul add 1 sub } {dup mul exch dup mul add 1 exch sub }ifelse } def % % Line function % /FMSpotFunction { pop } def % % Elipse function % /FMSpotFunction { dup 5 mul 8 div mul exch dup mul exch add % sqrt 1 exch sub } def % % /FMversion (4.0) def /FMLevel1 /languagelevel where {pop languagelevel} {1} ifelse 2 lt def /FMPColor FMLevel1 { false /colorimage where {pop pop true} if } { true } ifelse def /FrameDict 400 dict def systemdict /errordict known not {/errordict 10 dict def errordict /rangecheck {stop} put} if % The readline in PS 23.0 doesn't recognize cr's as nl's on AppleTalk FrameDict /tmprangecheck errordict /rangecheck get put errordict /rangecheck {FrameDict /bug true put} put FrameDict /bug false put mark % Some PS machines read past the CR, so keep the following 3 lines together! currentfile 5 string readline 00 0000000000 cleartomark errordict /rangecheck FrameDict /tmprangecheck get put FrameDict /bug get { /readline { /gstring exch def /gfile exch def /gindex 0 def { gfile read pop dup 10 eq {exit} if dup 13 eq {exit} if gstring exch gindex exch put /gindex gindex 1 add def } loop pop gstring 0 gindex getinterval true } bind def } if /FMshowpage /showpage load def /FMquit /quit load def /FMFAILURE { dup = flush FMshowpage /Helvetica findfont 12 scalefont setfont 72 200 moveto show FMshowpage FMquit } def /FMVERSION { FMversion ne { (Frame product version does not match ps_prolog!) FMFAILURE } if } def /FMBADEPSF { (PostScript Lang. Ref. Man., 2nd Ed., H.2.4 says EPS must not call X ) dup dup (X) search pop exch pop exch pop length 4 -1 roll putinterval FMFAILURE } def /FMLOCAL { FrameDict begin 0 def end } def /concatprocs { /proc2 exch cvlit def/proc1 exch cvlit def/newproc proc1 length proc2 length add array def newproc 0 proc1 putinterval newproc proc1 length proc2 putinterval newproc cvx }def FrameDict begin /FMnone 0 def /FMcyan 1 def /FMmagenta 2 def /FMyellow 3 def /FMblack 4 def /FMcustom 5 def /FrameNegative false def /FrameSepIs FMnone def /FrameSepBlack 0 def /FrameSepYellow 0 def /FrameSepMagenta 0 def /FrameSepCyan 0 def /FrameSepRed 1 def /FrameSepGreen 1 def /FrameSepBlue 1 def /FrameCurGray 1 def /FrameCurPat null def /FrameCurColors [ 0 0 0 1 0 0 0 ] def /FrameColorEpsilon .001 def /eqepsilon { sub dup 0 lt {neg} if FrameColorEpsilon le } bind def /FrameCmpColorsCMYK { 2 copy 0 get exch 0 get eqepsilon { 2 copy 1 get exch 1 get eqepsilon { 2 copy 2 get exch 2 get eqepsilon { 3 get exch 3 get eqepsilon } {pop pop false} ifelse }{pop pop false} ifelse } {pop pop false} ifelse } bind def /FrameCmpColorsRGB { 2 copy 4 get exch 0 get eqepsilon { 2 copy 5 get exch 1 get eqepsilon { 6 get exch 2 get eqepsilon }{pop pop false} ifelse } {pop pop false} ifelse } bind def /RGBtoCMYK { 1 exch sub 3 1 roll 1 exch sub 3 1 roll 1 exch sub 3 1 roll 3 copy 2 copy le { pop } { exch pop } ifelse 2 copy le { pop } { exch pop } ifelse dup dup dup 6 1 roll 4 1 roll 7 1 roll sub 6 1 roll sub 5 1 roll sub 4 1 roll } bind def /CMYKtoRGB { dup dup 4 -1 roll add 5 1 roll 3 -1 roll add 4 1 roll add 1 exch sub dup 0 lt {pop 0} if 3 1 roll 1 exch sub dup 0 lt {pop 0} if exch 1 exch sub dup 0 lt {pop 0} if exch } bind def /FrameSepInit { 1.0 RealSetgray } bind def /FrameSetSepColor { /FrameSepBlue exch def /FrameSepGreen exch def /FrameSepRed exch def /FrameSepBlack exch def /FrameSepYellow exch def /FrameSepMagenta exch def /FrameSepCyan exch def /FrameSepIs FMcustom def setCurrentScreen } bind def /FrameSetCyan { /FrameSepBlue 1.0 def /FrameSepGreen 1.0 def /FrameSepRed 0.0 def /FrameSepBlack 0.0 def /FrameSepYellow 0.0 def /FrameSepMagenta 0.0 def /FrameSepCyan 1.0 def /FrameSepIs FMcyan def setCurrentScreen } bind def /FrameSetMagenta { /FrameSepBlue 1.0 def /FrameSepGreen 0.0 def /FrameSepRed 1.0 def /FrameSepBlack 0.0 def /FrameSepYellow 0.0 def /FrameSepMagenta 1.0 def /FrameSepCyan 0.0 def /FrameSepIs FMmagenta def setCurrentScreen } bind def /FrameSetYellow { /FrameSepBlue 0.0 def /FrameSepGreen 1.0 def /FrameSepRed 1.0 def /FrameSepBlack 0.0 def /FrameSepYellow 1.0 def /FrameSepMagenta 0.0 def /FrameSepCyan 0.0 def /FrameSepIs FMyellow def setCurrentScreen } bind def /FrameSetBlack { /FrameSepBlue 0.0 def /FrameSepGreen 0.0 def /FrameSepRed 0.0 def /FrameSepBlack 1.0 def /FrameSepYellow 0.0 def /FrameSepMagenta 0.0 def /FrameSepCyan 0.0 def /FrameSepIs FMblack def setCurrentScreen } bind def /FrameNoSep { /FrameSepIs FMnone def setCurrentScreen } bind def /FrameSetSepColors { FrameDict begin [ exch 1 add 1 roll ] /FrameSepColors exch def end } bind def /FrameColorInSepListCMYK { FrameSepColors { exch dup 3 -1 roll FrameCmpColorsCMYK { pop true exit } if } forall dup true ne {pop false} if } bind def /FrameColorInSepListRGB { FrameSepColors { exch dup 3 -1 roll FrameCmpColorsRGB { pop true exit } if } forall dup true ne {pop false} if } bind def /RealSetgray /setgray load def /RealSetrgbcolor /setrgbcolor load def /RealSethsbcolor /sethsbcolor load def end /setgray { FrameDict begin FrameSepIs FMnone eq { RealSetgray } { FrameSepIs FMblack eq { RealSetgray } { FrameSepIs FMcustom eq FrameSepRed 0 eq and FrameSepGreen 0 eq and FrameSepBlue 0 eq and { RealSetgray } { 1 RealSetgray pop } ifelse } ifelse } ifelse end } bind def /setrgbcolor { FrameDict begin FrameSepIs FMnone eq { RealSetrgbcolor } { 3 copy [ 4 1 roll ] FrameColorInSepListRGB { FrameSepBlue eq exch FrameSepGreen eq and exch FrameSepRed eq and { 0 } { 1 } ifelse } { FMPColor { RealSetrgbcolor currentcmykcolor } { RGBtoCMYK } ifelse FrameSepIs FMblack eq {1.0 exch sub 4 1 roll pop pop pop} { FrameSepIs FMyellow eq {pop 1.0 exch sub 3 1 roll pop pop} { FrameSepIs FMmagenta eq {pop pop 1.0 exch sub exch pop } { FrameSepIs FMcyan eq {pop pop pop 1.0 exch sub } {pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse } ifelse RealSetgray } ifelse end } bind def /sethsbcolor { FrameDict begin FrameSepIs FMnone eq { RealSethsbcolor } { RealSethsbcolor currentrgbcolor setrgbcolor } ifelse end } bind def FrameDict begin /setcmykcolor where { pop /RealSetcmykcolor /setcmykcolor load def } { /RealSetcmykcolor { 4 1 roll 3 { 3 index add 0 max 1 min 1 exch sub 3 1 roll} repeat setrgbcolor pop } bind def } ifelse userdict /setcmykcolor { FrameDict begin FrameSepIs FMnone eq { RealSetcmykcolor } { 4 copy [ 5 1 roll ] FrameColorInSepListCMYK { FrameSepBlack eq exch FrameSepYellow eq and exch FrameSepMagenta eq and exch FrameSepCyan eq and { 0 } { 1 } ifelse } { FrameSepIs FMblack eq {1.0 exch sub 4 1 roll pop pop pop} { FrameSepIs FMyellow eq {pop 1.0 exch sub 3 1 roll pop pop} { FrameSepIs FMmagenta eq {pop pop 1.0 exch sub exch pop } { FrameSepIs FMcyan eq {pop pop pop 1.0 exch sub } {pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse } ifelse RealSetgray } ifelse end } bind put FMLevel1 not { /patProcDict 5 dict dup begin <0f1e3c78f0e1c387> { 3 setlinewidth -1 -1 moveto 9 9 lineto stroke 4 -4 moveto 12 4 lineto stroke -4 4 moveto 4 12 lineto stroke} bind def <0f87c3e1f0783c1e> { 3 setlinewidth -1 9 moveto 9 -1 lineto stroke -4 4 moveto 4 -4 lineto stroke 4 12 moveto 12 4 lineto stroke} bind def <8142241818244281> { 1 setlinewidth -1 9 moveto 9 -1 lineto stroke -1 -1 moveto 9 9 lineto stroke } bind def <03060c183060c081> { 1 setlinewidth -1 -1 moveto 9 9 lineto stroke 4 -4 moveto 12 4 lineto stroke -4 4 moveto 4 12 lineto stroke} bind def <8040201008040201> { 1 setlinewidth -1 9 moveto 9 -1 lineto stroke -4 4 moveto 4 -4 lineto stroke 4 12 moveto 12 4 lineto stroke} bind def end def /patDict 15 dict dup begin /PatternType 1 def /PaintType 2 def /TilingType 3 def /BBox [ 0 0 8 8 ] def /XStep 8 def /YStep 8 def /PaintProc { begin patProcDict bstring known { patProcDict bstring get exec } { 8 8 true [1 0 0 -1 0 8] bstring imagemask } ifelse end } bind def end def } if /combineColor { FrameSepIs FMnone eq { graymode FMLevel1 or not { [/Pattern [/DeviceCMYK]] setcolorspace FrameCurColors 0 4 getinterval aload pop FrameCurPat setcolor } { FrameCurColors 3 get 1.0 ge { FrameCurGray RealSetgray } { FMPColor graymode and { 0 1 3 { FrameCurColors exch get 1 FrameCurGray sub mul } for RealSetcmykcolor } { 4 1 6 { FrameCurColors exch get graymode { 1 exch sub 1 FrameCurGray sub mul 1 exch sub } { 1.0 lt {FrameCurGray} {1} ifelse } ifelse } for RealSetrgbcolor } ifelse } ifelse } ifelse } { FrameCurColors 0 4 getinterval aload FrameColorInSepListCMYK { FrameSepBlack eq exch FrameSepYellow eq and exch FrameSepMagenta eq and exch FrameSepCyan eq and FrameSepIs FMcustom eq and { FrameCurGray } { 1 } ifelse } { FrameSepIs FMblack eq {FrameCurGray 1.0 exch sub mul 1.0 exch sub 4 1 roll pop pop pop} { FrameSepIs FMyellow eq {pop FrameCurGray 1.0 exch sub mul 1.0 exch sub 3 1 roll pop pop} { FrameSepIs FMmagenta eq {pop pop FrameCurGray 1.0 exch sub mul 1.0 exch sub exch pop } { FrameSepIs FMcyan eq {pop pop pop FrameCurGray 1.0 exch sub mul 1.0 exch sub } {pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse } ifelse graymode FMLevel1 or not { [/Pattern [/DeviceGray]] setcolorspace FrameCurPat setcolor } { graymode not FMLevel1 and { dup 1 lt {pop FrameCurGray} if } if RealSetgray } ifelse } ifelse } bind def /savematrix { orgmatrix currentmatrix pop } bind def /restorematrix { orgmatrix setmatrix } bind def /dmatrix matrix def /dpi 72 0 dmatrix defaultmatrix dtransform dup mul exch dup mul add sqrt def /freq dpi dup 72 div round dup 0 eq {pop 1} if 8 mul div def /sangle 1 0 dmatrix defaultmatrix dtransform exch atan def /dpiranges [ 2540 2400 1693 1270 1200 635 600 0 ] def /CMLowFreqs [ 100.402 94.8683 89.2289 100.402 94.8683 66.9349 63.2456 47.4342 ] def /YLowFreqs [ 95.25 90.0 84.65 95.25 90.0 70.5556 66.6667 50.0 ] def /KLowFreqs [ 89.8026 84.8528 79.8088 89.8026 84.8528 74.8355 70.7107 53.033 ] def /CLowAngles [ 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 ] def /MLowAngles [ 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 ] def /YLowTDot [ true true false true true false false false ] def /CMHighFreqs [ 133.87 126.491 133.843 108.503 102.523 100.402 94.8683 63.2456 ] def /YHighFreqs [ 127.0 120.0 126.975 115.455 109.091 95.25 90.0 60.0 ] def /KHighFreqs [ 119.737 113.137 119.713 128.289 121.218 89.8026 84.8528 63.6395 ] def /CHighAngles [ 71.5651 71.5651 71.5651 70.0169 70.0169 71.5651 71.5651 71.5651 ] def /MHighAngles [ 18.4349 18.4349 18.4349 19.9831 19.9831 18.4349 18.4349 18.4349 ] def /YHighTDot [ false false true false false true true false ] def /PatFreq [ 10.5833 10.0 9.4055 10.5833 10.0 10.5833 10.0 9.375 ] def /screenIndex { 0 1 dpiranges length 1 sub { dup dpiranges exch get 1 sub dpi le {exit} {pop} ifelse } for } bind def /getCyanScreen { FMUseHighFrequencyScreens { CHighAngles CMHighFreqs} {CLowAngles CMLowFreqs} ifelse screenIndex dup 3 1 roll get 3 1 roll get /FMSpotFunction load } bind def /getMagentaScreen { FMUseHighFrequencyScreens { MHighAngles CMHighFreqs } {MLowAngles CMLowFreqs} ifelse screenIndex dup 3 1 roll get 3 1 roll get /FMSpotFunction load } bind def /getYellowScreen { FMUseHighFrequencyScreens { YHighTDot YHighFreqs} { YLowTDot YLowFreqs } ifelse screenIndex dup 3 1 roll get 3 1 roll get { 3 div {2 { 1 add 2 div 3 mul dup floor sub 2 mul 1 sub exch} repeat FMSpotFunction } } {/FMSpotFunction load } ifelse 0.0 exch } bind def /getBlackScreen { FMUseHighFrequencyScreens { KHighFreqs } { KLowFreqs } ifelse screenIndex get 45.0 /FMSpotFunction load } bind def /getSpotScreen { getBlackScreen } bind def /getCompositeScreen { getBlackScreen } bind def /FMSetScreen FMLevel1 { /setscreen load }{ { 8 dict begin /HalftoneType 1 def /SpotFunction exch def /Angle exch def /Frequency exch def /AccurateScreens FMUseAcccurateScreens def currentdict end sethalftone } bind } ifelse def /setDefaultScreen { FMPColor { orgrxfer cvx orggxfer cvx orgbxfer cvx orgxfer cvx setcolortransfer } { orgxfer cvx settransfer } ifelse orgfreq organgle orgproc cvx setscreen } bind def /setCurrentScreen { FrameSepIs FMnone eq { FMUseDefaultNoSeparationScreen { setDefaultScreen } { getCompositeScreen FMSetScreen } ifelse } { FrameSepIs FMcustom eq { FMUseDefaultSpotSeparationScreen { setDefaultScreen } { getSpotScreen FMSetScreen } ifelse } { FMUseDefaultProcessSeparationScreen { setDefaultScreen } { FrameSepIs FMcyan eq { getCyanScreen FMSetScreen } { FrameSepIs FMmagenta eq { getMagentaScreen FMSetScreen } { FrameSepIs FMyellow eq { getYellowScreen FMSetScreen } { getBlackScreen FMSetScreen } ifelse } ifelse } ifelse } ifelse } ifelse } ifelse } bind def end /gstring FMLOCAL /gfile FMLOCAL /gindex FMLOCAL /orgrxfer FMLOCAL /orggxfer FMLOCAL /orgbxfer FMLOCAL /orgxfer FMLOCAL /orgproc FMLOCAL /orgrproc FMLOCAL /orggproc FMLOCAL /orgbproc FMLOCAL /organgle FMLOCAL /orgrangle FMLOCAL /orggangle FMLOCAL /orgbangle FMLOCAL /orgfreq FMLOCAL /orgrfreq FMLOCAL /orggfreq FMLOCAL /orgbfreq FMLOCAL /yscale FMLOCAL /xscale FMLOCAL /edown FMLOCAL /manualfeed FMLOCAL /paperheight FMLOCAL /paperwidth FMLOCAL /FMDOCUMENT { array /FMfonts exch def /#copies exch def FrameDict begin 0 ne /manualfeed exch def /paperheight exch def /paperwidth exch def 0 ne /FrameNegative exch def 0 ne /edown exch def /yscale exch def /xscale exch def FMLevel1 { manualfeed {setmanualfeed} if /FMdicttop countdictstack 1 add def /FMoptop count def setpapername manualfeed {true} {papersize} ifelse {manualpapersize} {false} ifelse {desperatepapersize} {false} ifelse { (Can't select requested paper size for Frame print job!) FMFAILURE } if count -1 FMoptop {pop pop} for countdictstack -1 FMdicttop {pop end} for } {{1 dict dup /PageSize [paperwidth paperheight]put setpagedevice}stopped { (Can't select requested paper size for Frame print job!) FMFAILURE } if {1 dict dup /ManualFeed manualfeed put setpagedevice } stopped pop } ifelse FMPColor { currentcolorscreen cvlit /orgproc exch def /organgle exch def /orgfreq exch def cvlit /orgbproc exch def /orgbangle exch def /orgbfreq exch def cvlit /orggproc exch def /orggangle exch def /orggfreq exch def cvlit /orgrproc exch def /orgrangle exch def /orgrfreq exch def currentcolortransfer FrameNegative { 1 1 4 { pop { 1 exch sub } concatprocs 4 1 roll } for 4 copy setcolortransfer } if cvlit /orgxfer exch def cvlit /orgbxfer exch def cvlit /orggxfer exch def cvlit /orgrxfer exch def } { currentscreen cvlit /orgproc exch def /organgle exch def /orgfreq exch def currenttransfer FrameNegative { { 1 exch sub } concatprocs dup settransfer } if cvlit /orgxfer exch def } ifelse end } def /pagesave FMLOCAL /orgmatrix FMLOCAL /landscape FMLOCAL /pwid FMLOCAL /FMBEGINPAGE { FrameDict begin /pagesave save def 3.86 setmiterlimit /landscape exch 0 ne def landscape { 90 rotate 0 exch dup /pwid exch def neg translate pop }{ pop /pwid exch def } ifelse edown { [-1 0 0 1 pwid 0] concat } if 0 0 moveto paperwidth 0 lineto paperwidth paperheight lineto 0 paperheight lineto 0 0 lineto 1 setgray fill xscale yscale scale /orgmatrix matrix def gsave } def /FMENDPAGE { grestore pagesave restore end showpage } def /FMFONTDEFINE { FrameDict begin findfont ReEncode 1 index exch definefont FMfonts 3 1 roll put end } def /FMFILLS { FrameDict begin dup array /fillvals exch def dict /patCache exch def end } def /FMFILL { FrameDict begin fillvals 3 1 roll put end } def /FMNORMALIZEGRAPHICS { newpath 0.0 0.0 moveto 1 setlinewidth 0 setlinecap 0 0 0 sethsbcolor 0 setgray } bind def /fx FMLOCAL /fy FMLOCAL /fh FMLOCAL /fw FMLOCAL /llx FMLOCAL /lly FMLOCAL /urx FMLOCAL /ury FMLOCAL /FMBEGINEPSF { end /FMEPSF save def /showpage {} def % See Adobe's "PostScript Language Reference Manual, 2nd Edition", page 714. % "...the following operators MUST NOT be used in an EPS file:" (emphasis ours) /banddevice {(banddevice) FMBADEPSF} def /clear {(clear) FMBADEPSF} def /cleardictstack {(cleardictstack) FMBADEPSF} def /copypage {(copypage) FMBADEPSF} def /erasepage {(erasepage) FMBADEPSF} def /exitserver {(exitserver) FMBADEPSF} def /framedevice {(framedevice) FMBADEPSF} def /grestoreall {(grestoreall) FMBADEPSF} def /initclip {(initclip) FMBADEPSF} def /initgraphics {(initgraphics) FMBADEPSF} def /initmatrix {(initmatrix) FMBADEPSF} def /quit {(quit) FMBADEPSF} def /renderbands {(renderbands) FMBADEPSF} def /setglobal {(setglobal) FMBADEPSF} def /setpagedevice {(setpagedevice) FMBADEPSF} def /setshared {(setshared) FMBADEPSF} def /startjob {(startjob) FMBADEPSF} def /lettertray {(lettertray) FMBADEPSF} def /letter {(letter) FMBADEPSF} def /lettersmall {(lettersmall) FMBADEPSF} def /11x17tray {(11x17tray) FMBADEPSF} def /11x17 {(11x17) FMBADEPSF} def /ledgertray {(ledgertray) FMBADEPSF} def /ledger {(ledger) FMBADEPSF} def /legaltray {(legaltray) FMBADEPSF} def /legal {(legal) FMBADEPSF} def /statementtray {(statementtray) FMBADEPSF} def /statement {(statement) FMBADEPSF} def /executivetray {(executivetray) FMBADEPSF} def /executive {(executive) FMBADEPSF} def /a3tray {(a3tray) FMBADEPSF} def /a3 {(a3) FMBADEPSF} def /a4tray {(a4tray) FMBADEPSF} def /a4 {(a4) FMBADEPSF} def /a4small {(a4small) FMBADEPSF} def /b4tray {(b4tray) FMBADEPSF} def /b4 {(b4) FMBADEPSF} def /b5tray {(b5tray) FMBADEPSF} def /b5 {(b5) FMBADEPSF} def FMNORMALIZEGRAPHICS [/fy /fx /fh /fw /ury /urx /lly /llx] {exch def} forall fx fw 2 div add fy fh 2 div add translate rotate fw 2 div neg fh 2 div neg translate fw urx llx sub div fh ury lly sub div scale llx neg lly neg translate /FMdicttop countdictstack 1 add def /FMoptop count def } bind def /FMENDEPSF { count -1 FMoptop {pop pop} for countdictstack -1 FMdicttop {pop end} for FMEPSF restore FrameDict begin } bind def FrameDict begin /setmanualfeed { %%BeginFeature *ManualFeed True statusdict /manualfeed true put %%EndFeature } bind def /max {2 copy lt {exch} if pop} bind def /min {2 copy gt {exch} if pop} bind def /inch {72 mul} def /pagedimen { paperheight sub abs 16 lt exch paperwidth sub abs 16 lt and {/papername exch def} {pop} ifelse } bind def /papersizedict FMLOCAL /setpapername { /papersizedict 14 dict def papersizedict begin /papername /unknown def /Letter 8.5 inch 11.0 inch pagedimen /LetterSmall 7.68 inch 10.16 inch pagedimen /Tabloid 11.0 inch 17.0 inch pagedimen /Ledger 17.0 inch 11.0 inch pagedimen /Legal 8.5 inch 14.0 inch pagedimen /Statement 5.5 inch 8.5 inch pagedimen /Executive 7.5 inch 10.0 inch pagedimen /A3 11.69 inch 16.5 inch pagedimen /A4 8.26 inch 11.69 inch pagedimen /A4Small 7.47 inch 10.85 inch pagedimen /B4 10.125 inch 14.33 inch pagedimen /B5 7.16 inch 10.125 inch pagedimen end } bind def /papersize { papersizedict begin /Letter {lettertray letter} def /LetterSmall {lettertray lettersmall} def /Tabloid {11x17tray 11x17} def /Ledger {ledgertray ledger} def /Legal {legaltray legal} def /Statement {statementtray statement} def /Executive {executivetray executive} def /A3 {a3tray a3} def /A4 {a4tray a4} def /A4Small {a4tray a4small} def /B4 {b4tray b4} def /B5 {b5tray b5} def /unknown {unknown} def papersizedict dup papername known {papername} {/unknown} ifelse get end statusdict begin stopped end } bind def /manualpapersize { papersizedict begin /Letter {letter} def /LetterSmall {lettersmall} def /Tabloid {11x17} def /Ledger {ledger} def /Legal {legal} def /Statement {statement} def /Executive {executive} def /A3 {a3} def /A4 {a4} def /A4Small {a4small} def /B4 {b4} def /B5 {b5} def /unknown {unknown} def papersizedict dup papername known {papername} {/unknown} ifelse get end stopped } bind def /desperatepapersize { statusdict /setpageparams known { paperwidth paperheight 0 1 statusdict begin {setpageparams} stopped end } {true} ifelse } bind def /DiacriticEncoding [ /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /space /exclam /quotedbl /numbersign /dollar /percent /ampersand /quotesingle /parenleft /parenright /asterisk /plus /comma /hyphen /period /slash /zero /one /two /three /four /five /six /seven /eight /nine /colon /semicolon /less /equal /greater /question /at /A /B /C /D /E /F /G /H /I /J /K /L /M /N /O /P /Q /R /S /T /U /V /W /X /Y /Z /bracketleft /backslash /bracketright /asciicircum /underscore /grave /a /b /c /d /e /f /g /h /i /j /k /l /m /n /o /p /q /r /s /t /u /v /w /x /y /z /braceleft /bar /braceright /asciitilde /.notdef /Adieresis /Aring /Ccedilla /Eacute /Ntilde /Odieresis /Udieresis /aacute /agrave /acircumflex /adieresis /atilde /aring /ccedilla /eacute /egrave /ecircumflex /edieresis /iacute /igrave /icircumflex /idieresis /ntilde /oacute /ograve /ocircumflex /odieresis /otilde /uacute /ugrave /ucircumflex /udieresis /dagger /.notdef /cent /sterling /section /bullet /paragraph /germandbls /registered /copyright /trademark /acute /dieresis /.notdef /AE /Oslash /.notdef /.notdef /.notdef /.notdef /yen /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /ordfeminine /ordmasculine /.notdef /ae /oslash /questiondown /exclamdown /logicalnot /.notdef /florin /.notdef /.notdef /guillemotleft /guillemotright /ellipsis /.notdef /Agrave /Atilde /Otilde /OE /oe /endash /emdash /quotedblleft /quotedblright /quoteleft /quoteright /.notdef /.notdef /ydieresis /Ydieresis /fraction /currency /guilsinglleft /guilsinglright /fi /fl /daggerdbl /periodcentered /quotesinglbase /quotedblbase /perthousand /Acircumflex /Ecircumflex /Aacute /Edieresis /Egrave /Iacute /Icircumflex /Idieresis /Igrave /Oacute /Ocircumflex /.notdef /Ograve /Uacute /Ucircumflex /Ugrave /dotlessi /circumflex /tilde /macron /breve /dotaccent /ring /cedilla /hungarumlaut /ogonek /caron ] def /ReEncode { dup length dict begin { 1 index /FID ne {def} {pop pop} ifelse } forall 0 eq {/Encoding DiacriticEncoding def} if currentdict end } bind def FMPColor { /BEGINBITMAPCOLOR { BITMAPCOLOR} def /BEGINBITMAPCOLORc { BITMAPCOLORc} def /BEGINBITMAPTRUECOLOR { BITMAPTRUECOLOR } def /BEGINBITMAPTRUECOLORc { BITMAPTRUECOLORc } def } { /BEGINBITMAPCOLOR { BITMAPGRAY} def /BEGINBITMAPCOLORc { BITMAPGRAYc} def /BEGINBITMAPTRUECOLOR { BITMAPTRUEGRAY } def /BEGINBITMAPTRUECOLORc { BITMAPTRUEGRAYc } def } ifelse /K { FMPrintAllColorsAsBlack { dup 1 eq 2 index 1 eq and 3 index 1 eq and not {7 {pop} repeat 0 0 0 1 0 0 0} if } if FrameCurColors astore pop combineColor } bind def /graymode true def /bwidth FMLOCAL /bpside FMLOCAL /bstring FMLOCAL /onbits FMLOCAL /offbits FMLOCAL /xindex FMLOCAL /yindex FMLOCAL /x FMLOCAL /y FMLOCAL /setPatternMode { FMLevel1 { /bwidth exch def /bpside exch def /bstring exch def /onbits 0 def /offbits 0 def freq sangle landscape {90 add} if {/y exch def /x exch def /xindex x 1 add 2 div bpside mul cvi def /yindex y 1 add 2 div bpside mul cvi def bstring yindex bwidth mul xindex 8 idiv add get 1 7 xindex 8 mod sub bitshift and 0 ne FrameNegative {not} if {/onbits onbits 1 add def 1} {/offbits offbits 1 add def 0} ifelse } setscreen offbits offbits onbits add div FrameNegative {1.0 exch sub} if /FrameCurGray exch def } { pop pop dup patCache exch known { patCache exch get } { dup patDict /bstring 3 -1 roll put patDict 9 PatFreq screenIndex get div dup matrix scale makepattern dup patCache 4 -1 roll 3 -1 roll put } ifelse /FrameCurGray 0 def /FrameCurPat exch def } ifelse /graymode false def combineColor } bind def /setGrayScaleMode { graymode not { /graymode true def FMLevel1 { setCurrentScreen } if } if /FrameCurGray exch def combineColor } bind def /normalize { transform round exch round exch itransform } bind def /dnormalize { dtransform round exch round exch idtransform } bind def /lnormalize { 0 dtransform exch cvi 2 idiv 2 mul 1 add exch idtransform pop } bind def /H { lnormalize setlinewidth } bind def /Z { setlinecap } bind def /PFill { graymode FMLevel1 or not { gsave 1 setgray eofill grestore } if } bind def /PStroke { graymode FMLevel1 or not { gsave 1 setgray stroke grestore } if stroke } bind def /fillvals FMLOCAL /X { fillvals exch get dup type /stringtype eq {8 1 setPatternMode} {setGrayScaleMode} ifelse } bind def /V { PFill gsave eofill grestore } bind def /Vclip { clip } bind def /Vstrk { currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /N { PStroke } bind def /Nclip { strokepath clip newpath } bind def /Nstrk { currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /M {newpath moveto} bind def /E {lineto} bind def /D {curveto} bind def /O {closepath} bind def /n FMLOCAL /L { /n exch def newpath normalize moveto 2 1 n {pop normalize lineto} for } bind def /Y { L closepath } bind def /x1 FMLOCAL /x2 FMLOCAL /y1 FMLOCAL /y2 FMLOCAL /R { /y2 exch def /x2 exch def /y1 exch def /x1 exch def x1 y1 x2 y1 x2 y2 x1 y2 4 Y } bind def /rad FMLOCAL /rarc {rad arcto } bind def /RR { /rad exch def normalize /y2 exch def /x2 exch def normalize /y1 exch def /x1 exch def mark newpath { x1 y1 rad add moveto x1 y2 x2 y2 rarc x2 y2 x2 y1 rarc x2 y1 x1 y1 rarc x1 y1 x1 y2 rarc closepath } stopped {x1 y1 x2 y2 R} if cleartomark } bind def /RRR { /rad exch def normalize /y4 exch def /x4 exch def normalize /y3 exch def /x3 exch def normalize /y2 exch def /x2 exch def normalize /y1 exch def /x1 exch def newpath normalize moveto mark { x2 y2 x3 y3 rarc x3 y3 x4 y4 rarc x4 y4 x1 y1 rarc x1 y1 x2 y2 rarc closepath } stopped {x1 y1 x2 y2 x3 y3 x4 y4 newpath moveto lineto lineto lineto closepath} if cleartomark } bind def /C { grestore gsave R clip setCurrentScreen } bind def /CP { grestore gsave Y clip setCurrentScreen } bind def /FMpointsize FMLOCAL /F { FMfonts exch get FMpointsize scalefont setfont } bind def /Q { /FMpointsize exch def F } bind def /T { moveto show } bind def /RF { rotate 0 ne {-1 1 scale} if } bind def /TF { gsave moveto RF show grestore } bind def /P { moveto 0 32 3 2 roll widthshow } bind def /PF { gsave moveto RF 0 32 3 2 roll widthshow grestore } bind def /S { moveto 0 exch ashow } bind def /SF { gsave moveto RF 0 exch ashow grestore } bind def /B { moveto 0 32 4 2 roll 0 exch awidthshow } bind def /BF { gsave moveto RF 0 32 4 2 roll 0 exch awidthshow grestore } bind def /G { gsave newpath normalize translate 0.0 0.0 moveto dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath PFill fill grestore } bind def /Gstrk { savematrix newpath 2 index 2 div add exch 3 index 2 div sub exch normalize 2 index 2 div sub exch 3 index 2 div add exch translate scale 0.0 0.0 1.0 5 3 roll arc restorematrix currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /Gclip { newpath savematrix normalize translate 0.0 0.0 moveto dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath clip newpath restorematrix } bind def /GG { gsave newpath normalize translate 0.0 0.0 moveto rotate dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath PFill fill grestore } bind def /GGclip { savematrix newpath normalize translate 0.0 0.0 moveto rotate dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath clip newpath restorematrix } bind def /GGstrk { savematrix newpath normalize translate 0.0 0.0 moveto rotate dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath restorematrix currentlinewidth exch setlinewidth PStroke setlinewidth } bind def /A { gsave savematrix newpath 2 index 2 div add exch 3 index 2 div sub exch normalize 2 index 2 div sub exch 3 index 2 div add exch translate scale 0.0 0.0 1.0 5 3 roll arc restorematrix PStroke grestore } bind def /Aclip { newpath savematrix normalize translate 0.0 0.0 moveto dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath strokepath clip newpath restorematrix } bind def /Astrk { Gstrk } bind def /AA { gsave savematrix newpath 3 index 2 div add exch 4 index 2 div sub exch normalize 3 index 2 div sub exch 4 index 2 div add exch translate rotate scale 0.0 0.0 1.0 5 3 roll arc restorematrix PStroke grestore } bind def /AAclip { savematrix newpath normalize translate 0.0 0.0 moveto rotate dnormalize scale 0.0 0.0 1.0 5 3 roll arc closepath strokepath clip newpath restorematrix } bind def /AAstrk { GGstrk } bind def /x FMLOCAL /y FMLOCAL /w FMLOCAL /h FMLOCAL /xx FMLOCAL /yy FMLOCAL /ww FMLOCAL /hh FMLOCAL /FMsaveobject FMLOCAL /FMoptop FMLOCAL /FMdicttop FMLOCAL /BEGINPRINTCODE { /FMdicttop countdictstack 1 add def /FMoptop count 7 sub def /FMsaveobject save def userdict begin /showpage {} def FMNORMALIZEGRAPHICS 3 index neg 3 index neg translate } bind def /ENDPRINTCODE { count -1 FMoptop {pop pop} for countdictstack -1 FMdicttop {pop end} for FMsaveobject restore } bind def /gn { 0 { 46 mul cf read pop 32 sub dup 46 lt {exit} if 46 sub add } loop add } bind def /str FMLOCAL /cfs { /str sl string def 0 1 sl 1 sub {str exch val put} for str def } bind def /ic [ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0223 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0223 0 {0 hx} {1 hx} {2 hx} {3 hx} {4 hx} {5 hx} {6 hx} {7 hx} {8 hx} {9 hx} {10 hx} {11 hx} {12 hx} {13 hx} {14 hx} {15 hx} {16 hx} {17 hx} {18 hx} {19 hx} {gn hx} {0} {1} {2} {3} {4} {5} {6} {7} {8} {9} {10} {11} {12} {13} {14} {15} {16} {17} {18} {19} {gn} {0 wh} {1 wh} {2 wh} {3 wh} {4 wh} {5 wh} {6 wh} {7 wh} {8 wh} {9 wh} {10 wh} {11 wh} {12 wh} {13 wh} {14 wh} {gn wh} {0 bl} {1 bl} {2 bl} {3 bl} {4 bl} {5 bl} {6 bl} {7 bl} {8 bl} {9 bl} {10 bl} {11 bl} {12 bl} {13 bl} {14 bl} {gn bl} {0 fl} {1 fl} {2 fl} {3 fl} {4 fl} {5 fl} {6 fl} {7 fl} {8 fl} {9 fl} {10 fl} {11 fl} {12 fl} {13 fl} {14 fl} {gn fl} ] def /sl FMLOCAL /val FMLOCAL /ws FMLOCAL /im FMLOCAL /bs FMLOCAL /cs FMLOCAL /len FMLOCAL /pos FMLOCAL /ms { /sl exch def /val 255 def /ws cfs /im cfs /val 0 def /bs cfs /cs cfs } bind def 400 ms /ip { is 0 cf cs readline pop { ic exch get exec add } forall pop } bind def /rip { bis ris copy pop is 0 cf cs readline pop { ic exch get exec add } forall pop pop ris gis copy pop dup is exch cf cs readline pop { ic exch get exec add } forall pop pop gis bis copy pop dup add is exch cf cs readline pop { ic exch get exec add } forall pop } bind def /wh { /len exch def /pos exch def ws 0 len getinterval im pos len getinterval copy pop pos len } bind def /bl { /len exch def /pos exch def bs 0 len getinterval im pos len getinterval copy pop pos len } bind def /s1 1 string def /fl { /len exch def /pos exch def /val cf s1 readhexstring pop 0 get def pos 1 pos len add 1 sub {im exch val put} for pos len } bind def /hx { 3 copy getinterval cf exch readhexstring pop pop } bind def /h FMLOCAL /w FMLOCAL /d FMLOCAL /lb FMLOCAL /bitmapsave FMLOCAL /is FMLOCAL /cf FMLOCAL /wbytes { dup dup 24 eq { pop pop 3 mul } { 8 eq {pop} {1 eq {7 add 8 idiv} {3 add 4 idiv} ifelse} ifelse } ifelse } bind def /BEGINBITMAPBWc { 1 {} COMMONBITMAPc } bind def /BEGINBITMAPGRAYc { 8 {} COMMONBITMAPc } bind def /BEGINBITMAP2BITc { 2 {} COMMONBITMAPc } bind def /COMMONBITMAPc { /r exch def /d exch def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /lb w d wbytes def sl lb lt {lb ms} if /bitmapsave save def r /is im 0 lb getinterval def ws 0 lb getinterval is copy pop /cf currentfile def w h d [w 0 0 h neg 0 h] {ip} image bitmapsave restore grestore } bind def /BEGINBITMAPBW { 1 {} COMMONBITMAP } bind def /BEGINBITMAPGRAY { 8 {} COMMONBITMAP } bind def /BEGINBITMAP2BIT { 2 {} COMMONBITMAP } bind def /COMMONBITMAP { /r exch def /d exch def gsave 3 index 2 div add exch 4 index 2 div add exch translate rotate 1 index 2 div neg 1 index 2 div neg translate scale /h exch def /w exch def /bitmapsave save def r /is w d wbytes string def /cf currentfile def w h d [w 0 0 h neg 0 h] {cf is readhexstring pop} image bitmapsave restore grestore } bind def /ngrayt 256 array def /nredt 256 array def /nbluet 256 array def /ngreent 256 array def /gryt FMLOCAL /blut FMLOCAL /grnt FMLOCAL /redt FMLOCAL /indx FMLOCAL /cynu FMLOCAL /magu FMLOCAL /yelu FMLOCAL /k FMLOCAL /u FMLOCAL FMLevel1 { /colorsetup { currentcolortransfer /gryt exch def /blut exch def /grnt ex