Date: Thu Apr 14 2005 - 00:30:00 PDT
---------- Forwarded message ----------
Date: Thu, 14 Apr 2005 10:50:53 +0300 (IDT)
To: Boon Chong Ang <BCANG@altera.com>
Subject: Re: verilog lrm question
That is a cute question.
I was not sure of the answer myself, so I checked 3 different simulators.
All gave me the same answer: the output has the same value as the input.
On Thu, 14 Apr 2005, Boon Chong Ang wrote:
> Hi Shalom,
> I come across your name in verilog 2005 drafting committee. I have
> question to ask regarding primitive gate function. For example,
> primitive gate like and,or,nor,xor,xnor allow 1 output and one or more
> inputs. So, when xor primitive gate is having single input, is the
> expected output is reduction xor or treat it as normal xor with single
> input as the functional output will be different and I can't find
> further declaration from verilog LRM.
> Sorry that I forget to introduce myself. My name is Ang Boon Chong from
> Altera IC Design department. Still a freshy in design field.
> Thank you & best regards,
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