Re: FW: New Mantis Issue #667 for V-1364

From: Joseph P. Skudlarek (Jskud@cypress.com)
Date: Wed Apr 20 2005 - 11:27:16 PDT

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    Please note that Bryant's earlier work, while great, was refined in some
    important ways -- we almost incorporated the earlier work (based on the
    description in Ullman's Computational Aspects of VLSI), but stopped when
    we learned (from Randy Bryant) that it would give the wrong answers in
    important cases.

    Note that Tom Szymanski et. al. from Bells Labs had a wonderful and fast
    implementation of switch level simulation which they wrote up.

    If interested, I can dig up the exact references. /Jskud

    Shalom.Bresticker@freescale.com wrote:
    > When I did my Master's degree, I actually studied Bryant's Technical Report
    > cover to cover! (Of course, it was from 1978, not 1938.)
    >
    > Shalom
    >
    >
    > On Wed, 20 Apr 2005, Pragmatic C Software wrote:
    >
    >
    >>Quoting Shalom.Bresticker@freescale.com (Shalom.Bresticker@freescale.com):
    >>
    >>
    >>>Other than sequential UDPs, when is it wrong for primitives to evaluate
    >>>at time 0? If you already mentioned this, I'm sorry, I forgot.
    >>>
    >>>I agree that in most cases, terminal connections work like port connections,
    >>>but it needs to be stated. However, one exception, I think, is terminal
    >>>connections of switch-level primitives, where port collapsing on input
    >>>terminals, where possible, is required, not just optional. This is because
    >>>these primitives preserve strength information.
    >>>
    >>
    >> It turns out that "port collapsing on input" is not sufficient to
    >>model Verilog tran (switch level) gates because a relaxation algorithm
    >>is needed. The discussion of unspecified evaluation of tran channels
    >>is related to this. I think the original Gateway XL algorithm described
    >>in reference: Bryant, R. 'Switch-Level Model and Simulator for MOS
    >>Digital Systems', 1938 (it was a Cal Tech technical report but I think
    >>was also published in one of the IEEE Transactions).
    >>
    >> Related to this is the time 0 (we call it time minus infinity although
    >>it really is the delta just before time 0 starts) gate
    >>evaluation algorithm in Cver not only evaluates constants tied to
    >>gates and module input ports, but propagates the changes through the
    >>hierarchy, i.e. evaluate constants connected to gates (and continuous
    >>assignments), if the gate output connects to a port, treat it as a
    >>constant port connection and evaluation the strength preserving continuous
    >>assignment, etc. If the port, connects to a gate elsewhere in the hierarchy,
    >>treat it as a constant connection, etc.
    >>
    >> I think many old bipolar designs required this behavior. It evolved
    >>since for Cver we needed to match behavior from bug reports.
    >>
    >> Has Verilog changed since the 1990s in this area?
    >>/Steve
    >>
    >>
    >><... stuff removed>
    >>
    >>>--
    >>>Shalom.Bresticker @freescale.com Tel: +972 9 9522268
    >>>Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890
    >>>POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478
    >>>
    >>>[ ]Freescale Internal Use Only [ ]Freescale Confidential Proprietary
    >>>
    >>>
    >>
    >>
    >

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