Re: [sv-ec] Re: [sv-bc] potential command line option

From: Shalom.Bresticker@freescale.com
Date: Wed Apr 20 2005 - 20:02:45 PDT

  • Next message: Shalom.Bresticker@freescale.com: "Re: [sv-bc] potential command line option"

    Do they also find it strange that Verilog is not VHDL?

    Shalom

    On Wed, 20 Apr 2005, Brad Pierce wrote:

    > VHDL users may also find it strange that Verilog configurations
    > are not as general as VHDL configurations, that they can't be used to
    > change port mappings, etc.
    >
    > >Many people interested in using configs in Verilog are coming from a vhdl
    > >background, where configs are part of the language and could appear in
    > >the same file as other vhdl. They may find it strange that Verilog has
    > >a separate configuration language that is only allowed in separate files,
    > >and I am sure they will find it strange if it is only allowed in libmap
    > files.
    >
    > -- Brad
    >
    >
    > 

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