From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Wed Apr 20 2005 - 22:54:52 PDT
Hi, Brad -
Was this discussed and approved in committee meetings? (I missed a large
number of meetings and could have missed this discussion).
I would prefer required semicolons as originally intended and just fix all
my errors in the config section as previously noted.
Regards - Cliff
At 08:58 PM 4/20/2005, Brad Pierce wrote:
>In SystemVerilog these semicolons are optional.
>
> http://www.eda.org/sv/Changes_draft6/LRM_Changes_A_BNF.html
>
>-- Brad
>
>-----Original Message-----
>From: owner-btf@boyd.com [mailto:owner-btf@boyd.com]On Behalf Of
>Shalom.Bresticker@freescale.com
>Sent: Wednesday, April 20, 2005 8:22 PM
>To: Clifford E. Cummings
>Cc: btf@boyd.com; etf@boyd.com; sv-bc@eda.org; sv-ec@eda.org
>Subject: Re: Configs Intent - was: potential command line option
>
>
>Regarding the semicolons at the end of the statements, there is already an
>ETF
>issue on this. In fact, I think there are two. I think there is one issue
>(# 372 ?), which lists this as one of several config issues, and I think
>there
>is another one ( 5xx ? 501 ?) which is dedicated to this issue.
>
>Shalom
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training
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