RE: module foo ( .a(b), b); input b ; both become input !!

From: Steven Sharp (sharp@cadence.com)
Date: Thu Apr 21 2005 - 11:03:04 PDT

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    Another comment on this, from someone with even longer experience in
    Verilog, from Verilog-XL days:

    ------------- Begin Forwarded Message -------------

    From: "Scott Cranston" <cranston@cadence.com>

    I think a better way to approach this is to say:

    There is no such thing as an input or output port in Verilog - there are
    only ports, but there are input or output *signals* (wires, nets,
    whatever).

    module mm(.p({a,b}));
    input a; output b;

    What direction is p? This is why p is not declared input or output,
    since a port does not have that characteristic. For unnamed ports, ala

    module mm(a);
    input a;

    The port name is the same as the signal connected to it, but, still, the
    port itself does not have a direction, the signal a does.

    Your last paragraph below makes no sense, due to my previous statement,
    and also since you can't connect ports together inside modules:

    module mm(.p(a), .p(b)); <<--- illegal

    you can only connect the same signal to multiple ports, and in that case
    it does not matter how you declare the signal:

    module (.p(a), .q(a));
    [output a|input a|inout a]; <<- all three are legal

     -- Scott

    My last paragraph (which Scott says made no sense) was addressing the
    possibility that someone might have wanted the external ports to have
    direction, so they could declare

    module foo(.i(a), .o(a));
    input i;
    output o;
    wire a;
    endmodule

    However, even if this were legal, the ports would end up being collapsed,
    making i and o both inouts. So there would be no advantage to being able
    to declare their directions. If you wanted to ensure that nothing could
    drive backward from o to i, you would have to explicitly insert a continuous
    assignment. Once you do that, you are not connecting the same net to both
    ports. You can already do this with

    module foo (i, o);
    input i;
    output o;
    assign o = i;
    endmodule

    I was speculating on a possible argument for wanting to declare directions
    on the external ports, and showing that it was an invalid argument.

    Steven Sharp
    sharp@cadence.com

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