Re: Verilog-2001 $fullskew - HELP!

From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri May 06 2005 - 16:53:28 PDT

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    Hi, All -

    I received this encouraging feedback from Steve Wadsworth on the $fullskew
    issue (thanks to Steve for drudging up old painful memories to examine the
    issue).

    Regards - Cliff

    At 03:17 PM 5/6/2005, Steve_Wadsworth@amis.com wrote:
    >Cliff,
    >
    >Well, this was about as much fun as going to the dentist or going shopping
    >with my teenage daughters! Actually it wasn't that bad, but it took a
    >while to get back into the swing and remember what it was and should be. I
    >went through in detail each of Shalom's comments and feel that he has
    >covered the issue appropriately. Most all of his comments clarified the
    >spirit of the functionality and I don't remember if any really changed
    >functionality. I agree with Shalom on case 3 that there isn't really a
    >situation for it. Since it is a bi-directional check this would not apply
    >as it does in $timeskew. Also, I reviewed my draft copy of the VITAL 2001
    >standard to see what it said on functionality. We kept the actual
    >information in the text less verbose since we implemented it in the package
    >which was part of the standard. One thing that it had which would be a
    >good improvement for Verilog is a in-phase and an out-phase check. These
    >were two different checks. I'm not sure why I didn't push for this
    >addition since I was trying to ensure both standards had the same
    >capability as much as possible. I't was probably a factor of running out
    >of time since I know that there were other changes we would have liked to
    >make (wish I could remember them now- but when you are as old as I am you
    >are lucky to remember your name).
    >
    >The graphics are too small which may have caused the shift. I would make
    >the graphics larger so it is very clear where the edges are. I'm sure
    >that IEEE will then make them the size they want which may cause the same
    >problem again. I am happy to review any of this that you have questions
    >on.
    >
    >Steve

    ----------------------------------------------------
    Cliff Cummings - Sunburst Design, Inc.
    14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
    Phone: 503-641-8446 / FAX: 503-641-8486
    cliffc@sunburst-design.com / www.sunburst-design.com
    Expert Verilog, SystemVerilog, Synthesis and Verification Training



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