Survey - use-model for configs?

From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Tue May 10 2005 - 09:19:28 PDT

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    Subject: Survey - use-model for configs?
    (use-model survey question below)

    I am willing to scrap most of the config-file section to make configs more
    useable to the typical Verilog designer. I am willing to scrap or modify
    the following (they could all be added back in a later version of the
    standard if they are found to be useful and if they can be efficiently
    implemented by vendors):

    (1) Kill "..." directory wildcard (forces tools to potentially search
    inefficiently and compile too many files)
    (2) Modify wild cards to only find files with matching module names
    (like -y +libext)
    (3) Kill ":config" - this allowed configs to have the same name as
    modules. Kill it for now and add it back later if requested by users.
    (4) Kill "cell" - originally intended to allow users to read a library
    and then run a simulation such that every occurrence of and2.v in the
    design would be replaced with "myand2.v" or something like that.
    (5) And finally, change the keywords, if we must.
    (6) Is there more config-issues that cause tool-grief?? Kill-it!
    (7) Tools may want to support `ifdef and `define, but we should not add
    those to the spec this time.
    (8) Different call-options for lib.map (a) -L command line switch, (b)
    first file after the compile command (c) automatically read lib.map from
    the tool-invocation directory (all three could be legal)

    - Libraries that include libraries with file wildcards are extremely
    useful
    - Configs that call the top design, call default libraries and allow
    specific binding to a particular instance from a non-default library file
    is the important corner-case
    - Don't require that the user separately give file lists to the tools.

    In my mind, this covers 99% of the requirements of all users
    -------------------

    I know of two implementations of Verilog-2001 configs:

    Use-model #1 - library map-file is a separate file. Configs are part of the
    Verilog input stream. The user still must specify separately what files to
    compile.

    Use-model #2 - library and config are in the same file. Design files are
    separate. The user still must specify separately what files to compile.

    Which Verilog users are going to adopt these use models?

    Cliff's answer - only 1% (or less) of Verilog users will embrace either of
    these use-models. The 1% of designs that either use the non-standard
    `uselib or designs that need to call two different files for two different
    instances of the same module name.

    Configurations were suppose to be 100% useful to designers - current
    implementations fail to meet this goal.

    The library-map file: was supposed to indicate where the design files were
    located.

    The configuration file: in conjunction with the normal structure of modules
    and instances was supposed to indicate which files were needed to execute
    the design.

    If user has to still use command-line options to compile the files before
    coding two more files (library ad config), 99% of users will stick with the
    -v -y +libext switches and never touch configs.

    Implementation use models:

    Simple vendor #1 compiles all the library files every time the tool is
    called with a library map file (simple but not very efficient).

    Efficient vendor #2 uses the lib.map, config and design structure like a
    Makefile to do incremental compiles of files that need to be updated or
    that have not yet been compiled and does not compile unused models (more
    complex but very efficient).

    Comments? Please don't comment that we are out of time. Just comment on
    use-models as if we had time to do them over from scratch.

    Regards - Cliff

    ----------------------------------------------------
    Cliff Cummings - Sunburst Design, Inc.
    14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
    Phone: 503-641-8446 / FAX: 503-641-8486
    cliffc@sunburst-design.com / www.sunburst-design.com
    Expert Verilog, SystemVerilog, Synthesis and Verification Training

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