Is it a valid testcase

From: Kausik Datta (kausikd@cal.interrasystems.com)
Date: Fri May 13 2005 - 00:55:25 PDT

  • Next message: Steven Sharp: "Re: Is it a valid testcase"

    Hi,
    Is this a valid testcase?
    Diferent simulators behave differently. Does LRM say anything on this?
    I think this should be an error case.
    Thanks
    Kausik

    module used (.p(a),.q(a[0]));
    input [0:3] a;
    endmodule
     
    module user;
    wire [0:3] x;
    used inst1(.q(x[0]),.a(x)); // Should be error. As there is no port
    with the name a
    endmodule

     


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