Re: Is it a valid testcase

From: Shalom.Bresticker@freescale.com
Date: Mon May 16 2005 - 07:02:35 PDT

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    12.3.6 ("Connecting module instance ports by name") says,

    "The second way to connect module ports consists of explicitly linking the two names for each side of the connection, the port declaration name from the module declaration to the expression - the name used in the module declaration, followed by the name used in the instantiating module. This compound name is then placed in the list of module connections. The port name shall be the name specified in the module declaration. The port name cannot be a bit-select, a part-select, or a concatenation of ports. If the module port declaration was implicit, the port_expression shall be a simple identifier or escaped identifier, which shall be used as the port name. If the module port declaration was explicit, the explicit name is used as the name of port."

    Note the sentences,

    "The port name shall be the name specified in the module declaration."
    and
    "If the module port declaration was explicit, the explicit name is used as the name of port."

    I think that is explicit enough to say that the LRM defines this case as illegal.

    Shalom

    On Fri, 13 May 2005, Kausik Datta wrote:

    > Is this a valid testcase?
    > Diferent simulators behave differently. Does LRM say anything on this?
    > I think this should be an error case.
    > Thanks
    > Kausik
    >
    > module used (.p(a),.q(a[0]));
    > input [0:3] a;
    > endmodule
    >
    > module user;
    > wire [0:3] x;
    > used inst1(.q(x[0]),.a(x)); // Should be error. As there is no port
    > with the name a
    > endmodule 

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