IEEE 1364 Errata Task Force (ETF) Mailing List Archives
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Starting: Mon Jul 01 2002 - 07:17:46 PDT
Ending: Tue Oct 04 2005 - 16:11:56 PDT
- $fullskew
- $skew/$timeskew
- $timeskew
- 1364 Ballot Comment Review
- 1364 Ballot Comment Review meeting
- 1364 ballot response meeting tomorrow
- 1364 editorship
- 1364 mantis issues
- 1364 Meeting (telecon) on Wednesday, 4/27 at noon EDT
- 1364 Minutes - Mantis 680 Resolved
- 1364-2005 intro, index
- 14.2.4.3 grammar error
- [P1800] p1364-2005 introduction and clause numbering
- [P1800] SystemVerilog (P1800) and Verilog (P1364) Draft Documents Available
- [P1800] Updated Database
- [sv-bc] Keywords
- [sv-bc] potential command line option
- [sv-cc] Last 2 email votes for 1364
- [sv-cc] Mantis #658 (1364 Notes proposal) updated
- [sv-cc] P1364 Draft 7 (preliminary) available for review
- [sv-cc] P1364 meeting minutes and email ballot
- Boyd.com is moving - database & mail reflectors going offline
- Cancel Monday's meeting
- casez
- Cliff's Config Proposal #4 (simplification)
- close etf 658
- comment syntax
- Config facts & Dangerous Precedent - was: potential command line option
- Config-keyword work-around - was: potential command line option
- Configs & Modules in separate files - was: potential command line option
- Configs Intent - was: potential command line option
- Configs proposal version #1
- Configurations Proposal Version 2
- enhancement/350: Proposal to deprecate configs in Verilog source files
- enhancement/387: editing error in implementing proposal
- errata/428: PROPOSAL - 2.5.1: value of 16'shc, request for clarification
- errata/463: 4.1.13: Zero fill in ?: even if signed or x/z
- errata/465: PROPOSAL - 3.2, 3.6: net and variable initialization descriptions
- errata/486: PROPOSAL - 12.3.3: Implicit nets are not necessarily unsigned
- errata/549: 17.1.1.7 leading zeros in string format
- errata/618: 15.3.2: $timeskew Case 3 and Case 4 are the same
- errata/619: PROPOSAL - What is the width of a range with z and x's in the bounds?
- errata/639: PROPOSAL - fix use of "shall" and "may" by IEEE rules
- errata/644: A.8.2: attributes on system function calls
- errata/645: PROPOSAL - 7.1.2: pulldown strength specification ambiguity
- errata/647: Built-in functions use in constant expressions
- errata/648: Addition of Clause 2 is required
- errata/649: use of "unknown"
- errata/650: 9.7.6 does not explicitly say what happens if "wait" condition is x or z
- errata/651: 14.2.4.2, Example 2: last => should be *>
- errata/651: PROPOSAL - 14.2.4.2, Example 2: last => should be *>
- errata/652: 14.2.4.3, Example 2: path conditions not unique?
- errata/653: 2005D6, A.7.4: edge_sensitive_path_declaration should be in A.7.2
- errata/653: PROPOSAL - 2005D6, A.7.4: edge_sensitive_path_declaration should be in A.7.2
- errata/654: 14.2.3: specify block edge-sensitive path description with polarity
- errata/655: 2005D6, 7.1.6: ambiguities in instance array port connection rules
- errata/656: "port" vs. "terminal"
- errata/657: 14.5 Driving wired logic: error in Fig 14-6?
- errata/658: 14.5 Driving wired logic: error in Fig 14-6?
- errata/659: $fullskew
- errata/659: $fullskew bugs
- errata/659: errata $fullskew bugs
- errata/659: PROPOSAL - $fullskew bugs
- errata/660: Clause 7 does not clearly specify output of primitives with 1 input
- errata/661: 5.1.10,11: minor editorial
- errata/662: Incorrect rule in note on Table 4-21 in 4.4.1
- errata/663: Incorrect width extension rule in 4.1.10.
- errata/664: Missing rule for reduction operators in 4.5.1
- etf meeting
- Files are uploaded
- Final (I hope) P1800/D5 recirculation ballot draft
- Final IEEE P1800 & P1364 Drafts
- Final P1364/D7 for recirculation ballot
- IEEE Site for SystemVerilog & Verilog Drafts
- Is it a valid testcase
- Issue: Scope Rules (IEEE P1364-2005/D2, 5/26/03)
- Last 2 email votes for 1364
- leaving Freescale
- libmap/config file interpretation/experience
- Mantis #658 for V-1364: Notes
- meeting today?
- Miinutes from 1364 Issues Resolution Meeting 7-Apr05
- Minutes of the 1/10/04 ETF Meeting
- Minutes of the 1/24/05 ETF Meeting
- Minutes of the 2/7/05 Meeting
- module foo ( .a(b), b); input b ; both become input !!
- More on configs
- New configuration proposal uploaded
- New Mantis Issue #667 for V-1364
- No meeting on Monday
- P1364 Draft 7 (preliminary) available for review
- P1364 meeting minutes - 6th May, 2005
- p1364-2005 introduction and clause numbering
- pending/678
- potential command line option
- Process change for ballot editing issues
- Proposal for ETF erratum 350
- Proposal for Mantis 687, 1364 keyword compatibility
- Proposal for Mantis item 667
- references, bibliography (fwd)
- Reminder: 1364 Ballot Comment Review meeting
- Signedness of result of logical shift
- Some queries related to expression type
- Special 1364 Meeting to resolve Issue 680 (Configs)
- specify block edge-sensitive path description syntax question
- Survey - use-model for configs?
- SystemVerilog (P1800) and Verilog (P1364) Draft Documents Available
- Test
- Updated Database
- Updated proposals for Mantis 687, keyword compatibility
- Verilog Notes Review - Mantis 658
- Verilog-2001 $fullskew - HELP!
- What is $fullskew?
- What is label for a task
- what is the phone number to call into?
Last message date: Tue Oct 04 2005 - 16:11:56 PDT
Archived on: Tue Oct 04 2005 - 16:12:09 PDT
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