From: Dave Rich (David.Rich@synopsys.com)
Date: Mon Apr 05 2004 - 22:52:48 PDT
Thanks Kurt. I had anonymous unions on my mind and forgot the U. prefix
Cliff, see IEEE 1364-2001 section 7.10.1 "If two or more signals of
unequal strength combine in a wired net configuration, the stronger
signal shall
dominate all the weaker drivers and determine the result." In any case,
the point of the example was to show that the behavior of wires and
their drivers remain the same with this proposal. The data type of a
wire should only come in to play when converting the wire to an integral
value. For this reason, the data types that can be applied to a wire
should be limited to bit-stream types (types whose elements can be
concatenated together to form an integral value).
Dave
Kurt Baty wrote:
>On Mon, 2004-04-05 at 19:52, Clifford E. Cummings wrote:
>
>
>>>>For example, suppose I have the following explicit packed union:
>>>>
>>>>typedef struct packed {
>>>> bit [7:0] byteA;
>>>> reg [7:0] byteB;
>>>>} AB_t;
>>>>
>>>>union packed {
>>>> AB_t AB;
>>>> reg [15:0] V;
>>>>} U;
>>>>
>>>>initial begin
>>>> U.AB.byteA = 8'h55;
>>>> U.AB.byteB = 8'hzz;
>>>> V = V << 4;
>>>>
>>>>
>This line should be
>
> U.V = U.V << 4;
>
>
>
>>>> $displayh(V); // expect to see 5zz0
>>>>
>>>>
>This line should be
>
> $displayh(U.V);
>
>
>
>>>> $displayh({U.AB.byteA,U.AB.byteB}); // expect to see 50z0
>>>>
>>>>
>>>Is this supposed to be 55zz?
>>>
>>>
>>The first display of shifted V makes sense (5zz0)
>>The second display still seems like it should be 55zz. I don't understand
>>where the 50z0 comes from.
>>
>>
>>
>
>so if you
>
>$displayh(U.V[15:8]); you get 5z
>$displayh(U.V[7:0]); you get z0
>
>and if you
>
>$displayh(U.AB.byteA); you get 50 not 5z because it's bit (2-state)!!!
>$displayh(U.AB.byteB); you get z0
>
>so 50z0 OK?
>
>
>
>
>
>
-- -- David.Rich@Synopsys.com Technical Marketing Consultant and/or Principal Product Engineer http://www.SystemVerilog.org tele: 650-584-4026 cell: 510-589-2625
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