From: Alec Stanculescu (alec@fintronic.com)
Date: Thu Apr 29 2004 - 20:05:04 PDT
Harry,
You asked the following question which became issue 282:
>Given the following Verilog 2001 case,
>
> module test(A,B,C,Z);
> parameter AW = 4, BW = 5, CW = 7, ZW = 10;
> input [AW-1:0] A; // 4 bits
> input [BW-1:0] B; // 5 bits
> input [CW-1:0] C; // 7 bits
> output [ZW-1:0] Z; // 10 bits
>
> assign Z = $signed(A) * $signed(B) + $unsigned(C);
> endmodule
>
>What we are trying to determine is which implementation of (1),
> (2) or (3) below is correct according to the standard rules defined in the
> LRM of Verilog 2001? >
> (1) Perform "D = $signed(A)*$signed(B)" first,
> then truncates it to C's size, denoted as value E,
> then the assignment "Z = $unsigned(E) + $unsigned(C)"
>
> (2) Perform "D = $unsigned(A)*$unsigned(B)" first,
> then the assignment "Z = $unsigned(D) + $unsigned(C)"
>
> (3) Perform "D = $signed(A)*$signed(B)" first,
> then the assignment "Z = $signed(D) + $unsigned(C)"
>
In issue 282 the most relevant part of the LRM, which was omitted from
the discussion so far, is:
"4.5.1 Expression type depends only on the operands. It does not depend
on the LHS. "
Therefore, the first expression to evaluate is the
multiplication and the type of the expression depends only on the two
operands.
Also, we should be happy that the LRM is very clear on this issue and
that the correct interpretation is consistent with sound language
design which leads the following two excerpts to be equivalent:
"assign Z = $signed(A) * $signed(B) + $unsigned(C)"
is equivalent to
"assign D = $signed(A) * $signed(B);
assign Z = $signed(D) + $unsigned(B);
/* where D depends only on A and B as stipulated in 4.5.1*/"
It would have been a nightmare if the LRM would have stated any
different on this issue.
Regards,
Alec Stanculescu
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