From: Kathy McKinley (mckinley@cadence.com)
Date: Wed May 12 2004 - 18:20:08 PDT
Here is a first cut at an overview of the issues around specifying
2-state and 4-state datatypes in Verilog. We would like to provide
a clear and concise description of the issues for consideration by the BTF.
SPECIFYING 2-STATE AND 4-STATE DATATYPES
We would like to define both 2-state and 4-state primitive datatypes.
We need a way to specify these datatypes in various contexts, particularly
if we want to allow construction of more sophisticated datatypes, such as
a structure that contains both 2-state and 4-state members.
The issue of how to express the primitive logic type within the language
is at question. There are a number of alternatives:
1) Adopt the SystemVerilog keywords "bit" (2-state) and "logic" (4-state).
Advantages:
- These names are natural to hardware designers
- These names are compatible with SystemVerilog
Disadvantages:
- Both keywords are known to have conflicts with existing designs
(the downside of being "natural").
- People have different assumptions about the meaning of both names.
Even within the small datatypes subgroup, some would assume "bit"
to be 2-state, and others would assume it to be 4-state.
2) Choose very precise new names -- like "bit2s" and "bit4s" --
that would have little chance of conflict with existing designs.
Advantages:
- Small likelihood of keyword conflicts with existing designs
- Exact meaning is obvious
Disadvantages:
- SystemVeriog designs would not be compatible without modification
3) Use a mechanism other than a name, attributes for example.
Advantages:
- No keyword conflicts with existing designs
Disadvantages:
- Such a strategy would be more verbose, and possibly less clear,
than use of keywords
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