datatypes examples

From: Kathy McKinley (mckinley@cadence.com)
Date: Wed May 12 2004 - 19:48:25 PDT

  • Next message: Shalom.Bresticker@freescale.com: "Re: 2-state and 4-state names"

    EXAMPLE 1: A tagged vector (packet)

        typedef enum { PACKET_OK, PACKET_ERROR } status_t;

        typedef vect {
            [7:0] src_port; // number of the source port
            [7:0] dst_port; // number of the destination port
            status_t status; // status bit
            [127:0] payload; // packet payload
        } packet_t;

        packet_t packet; // an object of type packet

        initial
        begin
            packet.status = PACKET_OK;
            .
            .
            .

    Things to note:

        - The enumeration "status_t" defines named constants PACKET_OK and
          PACKET_ERROR for convenience. They have the values 0 and 1
          respectively.

        - The object "packet" is a 4-state Verilog bit vector, with all
          that implies (integral operations, bit selects, part selects, etc.).
          Anything that you can do with the following object:

              reg [144:0] another_packet;

          you can do with "packet" too. The only difference is that you can
          do something extra with "packet".

        - Because "packet" is a tagged vector, you can also refer to parts
          of the object by member name:
     
          The statement

              packet.status = PACKET_OK;

          is equivalent to

              packet[128] = 1'b0;

           You can look at a tagged vector as a combined vector/structure.

        - Because the logic type was unspecified, you can use "packet_t"
          to create both 2-state and 4-state objects. To minimize confusion
          (I hope), I am going to use the SystemVerilog keywords for these items,
          because that is what we have been using in our discussions. You
          simply precede the type name with a logic name to indicate
          the underlying logic:

              bit packet_t packet_2s; // a 2-state packet
              logic packet_t packet_4s; // a 4-state packet

          Because these objects are both bit vectors, you can do things like:

              packet_2s = packet_4s;
              packet_4s = packet_2s;

          Conversions will apply automatically.

    EXAMPLE 2: A structure (test_status)

        typedef struct {
            int warning_count;
            int error_count;
            real percent_complete;
        } counts_t;

        counts_t test_status;

        initial
        begin
            test_status.percent_complete = 0.0;
            .
            .
            .

    Things to note:

        - Object "test_status" is not a vector. You cannot use bit selects or
          part selects on it. It is very much like a C structure.

        - Object "test_status" is heterogeneous; it contains a mixture of
          integers and real numbers.

        - Type "counts_t" is strongly typed. Object "test_status" is compatible
          only with other objects of type "counts_t".

    A FINAL NOTE:

        - It is likely that the objects "packet" (from example 1) and
          "test_status" (from example 2) will be used in very different ways.
          Formally defining datatypes/operations that are consistent with
          these two different styles (homogeneous hardware-like and
          heterogeneous testbench-like) increases the likelihood that
          both styles will be optimized well in most implementations.

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