write-up for discussion of keyword for kinds of data

From: Dave Rich (David.Rich@synopsys.com)
Date: Thu May 27 2004 - 04:15:20 PDT

  • Next message: Shalom.Bresticker@freescale.com: "Re: write-up for discussion of keyword for kinds of data"

    Attached for our discussion today is my write-up describing
    orthogonality between kinds and data types.

    Also attached is my earlier e-mail to Kurt that hat a complete example 

    -- 
--
David.Rich@Synopsys.com
Technical Marketing Consultant and/or
Principal Product Engineer
http://www.SystemVerilog.org
tele:  650-584-4026
cell:  510-589-2625

    attached mail follows:

    Hi Kurt,

    If its not too late...

    A good reason to have packed structs behave as a 4-state vectors when
    used as a whole is that a packed struct is basically an implied union,
    and you want the behavior top match that of an explicit union.

    For example, suppose I have the following explicit union

    typedef struct packed {
        bit [7:0] byteA;
        reg [7:0] byteB;
    } AB_t;

    union packed {
        AB_t AB;
        reg [15:0] V;
    } U;

    initial begin
        U.AB.byteA = 8'h55;
        U.AB.byteB = 8'hzz;
        V = V << 4;
        $displayh(V); // I expect to see 5zz0

    Now lets take the implicit union version

    AB_t AB;
    initial begin
        AB.byteA = 8'h55;
        AB.byteB = 8'hzz;
        AB = AB << 4;
        $displayh(V); // I expect to see 5zz0

    AB as a whole is a 4-state bit vector that is in an implied union with
    the packed structure.

    I would like to see a similar approach with wires. A wire declared with
    a user defined type should behave as an implicit union between the wire
    net type and variable data type. This difference with the wires is that
    you always uses the net type for driving, and the variable type for
    reading. What this means is that you can have multiple drivers with
    different strengths on an wire with a user defined type, and the wire
    will be resolved using the standard rules for that net type. Its only
    when that wire needs to be cast to an integral expression that the
    variable type is used.

    For example, lets say I have a wire declared with the type AB_t above.

    wand <AB_t> ABw;
    pullup pA[7:1] (ABw.byteA[7:1]); // pullup all but bit 0
    pullup pB[7:1] (ABw.byteB[7:1]); // pullup all but bit 0
    buf (ABw.byteA[7],0); // will be 0 because strong0 overrides pull1
    buf (ABw.byteB[7],0); // will be 0 because strong0 overrides pull1
    buf (ABw.byteA[6],1'bx); // will be 0 because strongX overrides pull1,
    and X cast to 0
    buf (ABw.byteB[6],1'bx); // will be X because strongX overrides pull1
    buf (weak0,weak1) (ABw.byteA[5],0); // will be 1 because pull1 overrides
    weak0
    buf (weak0,weak1) (ABw.byteB[5],0); // will be 1 because pull1 overrides
    weak0
    buf (pull0,pull1) (ABw.byteA[4],0); // will be 0 because wire-and of 1 and 0
    buf (pull0,pull1) (ABw.byteB[4],0); // will be 0 because wire-and of 1 and 0
    buf (pull0,pull1) (ABw.byteA[3],1); // will be 1 because wire-and of 1 and 1
    buf (pull0,pull1) (ABw.byteB[3],1); // will be 1 because wire-and of 1 and 1
    buf (pull0,pull1) (ABw.byteA[3],1'bx); // will be 0 because wire-and of
    1 and x, cast to 0
    buf (pull0,pull1) (ABw.byteB[3],1'bx); // will be x because wire-and of
    1 and x
    initial #1 #1 for (i=7;i>=0;i=i-1) $display("%b %v %b %v ",
            ABw.byteA[i], ABw.byteA[i], ABw.byteB[i], ABw.byteB[i],,i);
    endmodule

    Will display
    0 St0 0 St0 7
    0 StX x StX 6
    1 Pu1 1 Pu1 5
    0 Pu0 0 Pu0 4
    0 PuX x PuX 3
    1 Pu1 1 Pu1 2
    1 Pu1 1 Pu1 1
    0 HiZ z HiZ 0

    Note that the only difference in the table above is the x and z is
    converted to 0 for binary representation of byteA.

    Dave 

    --
--
David.Rich@Synopsys.com
Technical Marketing Consultant and/or
Principal Product Engineer
http://www.SystemVerilog.org
tele:  650-584-4026
cell:  510-589-2625

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