Re: write-up for discussion of keyword for kinds of data

From: Kathy McKinley (mckinley@cadence.com)
Date: Thu May 27 2004 - 08:22:34 PDT

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    > Dave,
    >
    > > Attached for our discussion today is my write-up describing
    > > orthogonality between kinds and data types.
    > > Also attached is my earlier e-mail to Kurt that hat a complete example
    >
    > I read your write-up. I probably did not understand 100% everything on a
    > first reading, at least not as you intended it, but anyway...
    >
    > A problem I see with having 'reg' as a data type instead of a data kind
    > is that a generation of engineers has been taught to contrast wires and
    > regs. Now you would get that 'wire' is essentially the same as
    > 'wire reg'. That would be terribly confusing.
    >
    > Personally I never had much of a problem with confusing 'reg' with
    > 'register'. I looked at 'reg' as being similar to 'register' as being a
    > variable that gets assigned a new value at a specific time and retains
    > that value until assigned a new value.
    >
    > To change that now is unwise, I think.
    >
    > Shalom

    I agree with Shalom. If you look at the IEEE 2001 LRM, the discussion
    of "reg" and variables is fundamentally about what we have been calling
    the "data object kind". For those who do not have an LRM handy, I am
    appending the relative paragraphs from the LRM.

    Kathy

    3.0 Data types (p. 20)

    The set of Verilog HDL data types is designe to represent the data
    storage and transmission elements found in digital hardware.

    3.2 Nets and Variables (p.20)

    There are two main groups of data types: the variable data types and
    the net data types. These two groups differ in the way that they are
    assigned and hold values. They also represent different hardware structures.

    3.2.1 Net declarations (p. 20)

    The net data types shall represent physical connections between structural
    entities, such as gates. A net shall not store a value (except for the
    trireg net). Instead, its value shall be determined by the values of
    its drivesr, such as a continuous assignment or a gate. See section 6
    and 7, for definitions of these constructs ...

    ...

    3.8 regs (p. 31)

    Assignments to a reg are made by procedural assignments (see 6.2 and
    9.2). Since the reg holds a value between assignments, it can be used
    to model hardware registers. Edge-sensitive (i.e. flip-flops) and
    level sensitive (i.e. RS and transparent latches) storage elements
    can be modeled. A reg need not represent a hardware element since
    it can also be used to represent combinatorial logic.

    3.9 Integers, reals, times, and realtimes (p. 31)

    In addition to modeling hardware, there are other uses for variables
    in an HDL model. Although reg variables can be used for general
    purposes, such as counting the number of times a particular net
    changes value, the integer and time variable data types are provided
    for convenience and to make the description more self documenting.

    ...

    An integer is a general-purpose variable used for manipulating quantities
    that are not regarded as hardware registers.

    A time variable is used for storing and manipulating simulation time
    quantities in situations where timing checks are required and for
    diagnostics and debugging purposes. This data type is typically used
    in conjunction with the $time system function (see 17.).

    The integer and time variables shall be assigned values in the same
    manner as reg. Procedural assignments shall be used to trigger their
    value changes.

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