From: Kathy McKinley (mckinley@cadence.com)
Date: Fri Jul 23 2004 - 11:15:17 PDT
Attendees:
Kurt Baty
Shalom Bresticker
Francoise Martinolle
Kathy McKinley
Dave Rich
Stuart Sutherland
Action Items:
- Kathy to try to find out how we might make proposals
for continuing datatypes extensions in new IEEE setup
- Kathy to ask Steven Sharp to add agenda items to BTF meeting
Summary:
We spent the meeting discussing how we might proceed, given
the uncertainty in the new organization under IEEE. It appears
that there is no provision under consideration that would allow us
to continue our datatypes extensions in the short term.
Much of our current effort is focused on support for extended datatypes
on nets, an area that is not covered by 1364 or SystemVerilog. This is
a significant hole, and both Verilog and SystemVerilog users want this
capability. Datatype orthogonality and the corresponding extended support
that it would provide for nets was endorsed at the 1364 working group level.
If there is no forum in which to continue this work, then there is a risk
that different implementations will arise to fill this hole before we can
arrive at a common standard solution.
It is our understanding that the current goal is to have SystemVerilog
standardized with very little change. Is there some way that we can
propose a pipelined effort to continue the datatypes work, in a way
that will not interfere with the short-term IEEE goals? We would like
to discuss making a proposal for this at our next BTF meeting.
We also discussed the need for an integrated document at some point,
perhaps not immediately. This need is quite apparent in our current
datatypes work, where the description of object kinds (what it means
to be a parameter, variable, port) is in 1364, and the description of
new datatypes (bit, structs, etc.) is in SystemVerilog. In order to
properly discuss semantics of object kinds and the full set of datatypes,
we need to modify the text for both parts. The extensions, even if
they are made in two documents, need to be made by the same group.
Integrating the 1364 and SystemVerilog documents would be a big effort,
but it seems like it will be necessary at some point for making extensions.
Could we propose to split the IEEE document into several volumes, some
of which might be quite independent, and some of which would be the focus
of serious integration effort? A separate volume would be different
from a "dot standard" in that it would not be balloted separately.
Perhaps the integration could be phased in over different versions
of the standard. We would also like this document issue to be discussed
at the next BTF meeting.
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