Re: Proposal for a 'wone' net type

From: Krishna Garlapati (krishna@synplicity.com)
Date: Thu Nov 04 2004 - 11:26:58 PST

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    Shalom,

    I am not sure if any synthesis tools do parallel buffering to increase
    drive strengths. Synthesis tools (AFAIK) instead cascade buffers to increase
    drive strengths. Assuming some tools do that, I don't think there will be any
    error in the gate dumps since it "looses" all form and factor of RTL. For a
    gate dump routine, it'll look like 3 buffers driving a net which is legal Verilog.

    Your point is still valid of what happens when a user runs a verification
    tool of the gate dump versus original RTL. This might certainly be flagged
    as an error but the question is, didn't the user explicitly say so (wanted it)
    by using wone net type ??

    Thanks,
    - Krishna.

    Shalom.Bresticker@freescale.com wrote:
    > Hi,
    >
    > I have not been following the 'wone' discussion closely,
    > but I have a question about this:
    >
    > Suppose I really do something like
    >
    >
    >> module top;
    >> wone logic mout;
    >> ...
    >> mux m1(sel, in0, in1, mout);
    >> endmodule
    >
    >
    > Now suppose that within m1, in RTL, I really do have only one driver
    > so it is OK. Say mout is output of a buffer, for example.
    >
    > Now suppose I synthesize and there is a big load on this signal,
    > and in order to drive it with required timing, the synthesis tool
    > replaces this buffer with a couple of buffers in parallel,
    > all with the same input and connected to the same output.
    >
    > Logically it is equivalent to the original, but in the gate-level
    > netlist, I now have multiple drivers on this signal.
    > I would now get a compilation error.
    >
    > How would this be solved?
    > The point is that I don't want to have to write a second version of top.
    >
    > Thanks,
    > Shalom
    >

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