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------------------------------------------------------------------------
SECTION 4.1
CHANGE
An array is a collection of variables, all of the
same type, and accessed using the same name plus
one or more indices."
TO
An array is a collection of data objects, all of the
^^^^^^^^^^^^
same data type and kind, and accessed using the same name
^^^^^^^^^^^^^^^^^^
plus one or more indices.
------------------------------------------------------------------------
SECTION 4.2
CHANGE
SystemVerilog enhances fixed-size unpacked arrays
in that in addition to all other variable types,
unpacked arrays can also be made of object handles
(see Section 11.4) and events (see Section 13.5).
TO
SystemVerilog enhances fixed-size unpacked arrays
in that in addition to all other data types,
^^^^
unpacked arrays can also be made of object handles
(see Section 11.4) and events (see Section 13.5).
------------------------------------------------------------------------
SECTION 4.7
THE PARAGRAPH THAT PRECEDES THIS ONE IS GENERAL AND CORRECT,
NOW THAT NETS HAVE DATA TYPES. REMOVE:
An array of wires can be assigned to an array of
variables having the same number of unpacked dimensions
and the same length for each of those dimensions,
and vice-versa.
INTEGRATE WITH PRECEDING EXAMPLE:
wire [31:0] W [9:0];
assign W = A;
initial #10 B = W;
------------------------------------------------------------------------
SECTION 23.7
CHANGE
SystemVerilog provides system functions to return
information about a particular dimension of an array
variable or type.
TO
SystemVerilog provides system functions to return
information about a particular dimension of an array
data object or data type.
^^^^^^^^^^^ ^^^^
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