RE: [sv-bc] DataTypes: BNF changes

From: Steven Sharp (sharp@cadence.com)
Date: Wed Nov 10 2004 - 15:47:31 PST

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    >There is already a lexical restriction in Verilog for things like a
    >space between two ampersands:
    >
    >A & & B

    BTW, I looked for this restriction in the 1364 LRM to see if there was
    any useful wording, and did not find it. Apparently this is just a
    de fact standard based on the fact that Verilog-XL produces an error
    for it.

    Steven Sharp
    sharp@cadence.com

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