Re: uwire data type and System Verilog

From: Steven Sharp (sharp@cadence.com)
Date: Wed Nov 10 2004 - 17:55:03 PST

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    >Because variable input/output ports are allowed, the situation is more
    >complex in System Verilog. Consider this case:
    >
    >module top();
    >wire w;
    >mid u1(w);
    >mid u2(w);
    >endmodule
    >
    >module mid(output logic o);
    >bot u1(o);
    >endmodule
    >
    >module bot(output uwire o);
    >endmodule
    >
    >If the bot port is a wire rather than uwire, this is a perfectly
    >legal System Verilog design. With the uwire port on bot, is this
    >a legal design? Should it give any non-fatal error messages or
    >warnings?

    Here is my understanding of it. The wire top.w has two drivers,
    the continuous assignments from the port connections to u1 and u2.
    Since it is a wire, not a uwire, having two drivers does not produce
    an error. However, it is reasonable that it should warn that it
    didn't port collapse the connection from bot to mid, so the uwire
    requirements aren't being propagated. Is that what you were getting
    at?

    In Verilog it is sufficient to require port collapsing for net
    connections to uwires, to get full checking. This works because
    a sink in a port connection is always a net. This is no longer
    true in SystemVerilog.

    Steven Sharp
    sharp@cadence.com

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