[sv-bc] DataTypes: Minor LRM edits

From: Kathy McKinley (mckinley@cadence.com)
Date: Wed Nov 10 2004 - 18:11:38 PST

  • Next message: Shalom Bresticker: "Re: [sv-bc] DataTypes: BNF changes"

    Here are some suggested edits of the "less-critical" variety:

    ----------------------------------------------------------------------
    SECTION 4.2

    CHANGE:

    Packed arrays can only be made of the single bit types (bit,
    logic, reg, wire, and the other net types) and recursively
    other packed arrays and packed structures.

    TO:

    Packed arrays can be made of only the single bit types (bit,
    logic, reg) and recursively other packed arrays and packed
    structures.

    ----------------------------------------------------------------------
    Section 7.3

    CHANGE:

    The semantics of such an assignment expression are
    those of a function which evaluates the right hand side,
    casts the right hand side to the left hand data type,
    stacks it, updates the left hand side and returns the
    stacked value. The type returned is the type of the
    left hand side data type. If the left hand side is
    a concatenation, the type returned shall be an unsigned
    integral value whose bit length is the sum of the
    length of its operands.

    TO:

    The semantics of such an assignment expression are
    those of a function that evaluates the right hand side,
    casts the right hand side to the left hand side data type,
    stacks it, updates the left hand side and returns the
    stacked value. The data type of the value that is returned
    is the data type of the left hand side. If the left hand side is
    a concatenation, then the data type of the value that is returned
    shall be an unsigned integral data type whose bit length is the sum
    of the length of its operands.

    ----------------------------------------------------------------------
    SECTION 7.12

    CHANGE:

    SystemVerilog enhances the concatenation operation to allow concatenation
    of variables of type string. In general, if any of the operands is of
    type string, the concatenation is treated as a string, and all other
    arguments are implicitly converted to the string type (as described
    in Section 3.7). String concatenation is not allowed on the left hand
    side of an assignment, only as an expression.

    TO:

    SystemVerilog enhances the concatenation operation to allow concatenation
    of data objects of type string. In general, if any of the operands is of
       ^^^^^^^^^^^^
    the data type string, the concatenation is treated as a string, and all other
    ^^^^^^^^^^^^^
    arguments are implicitly converted to the string data type (as described
                                                     ^^^^
    in Section 3.7). String concatenation is not allowed on the left hand
    side of an assignment, only as an expression.

    CHANGE:

    The replication operator (also called a multiple concatenation) form
    of braces can also be used with variables of type string. In the case
    of string replication, a non-constant multiplier is allowed.

    TO:

    The replication operator (also called a multiple concatenation) form
    of braces can also be used with data objects of type string. In the case
                                    ^^^^^^^^^^^^
    of string replication, a non-constant multiplier is allowed.

    ----------------------------------------------------------------------
    SECTION 7.16

    CHANGE:

    Unpacked structure and array variables, literals, and
    expressions can all be used as aggregate expressions.

    TO:

    Unpacked structure and array data objects, literals, and
                                 ^^^^^^^^^^^^
    expressions can all be used as aggregate expressions.

    ----------------------------------------------------------------------
    SECTION 9.5

    CHANGE:

    SystemVerilog removes this restriction, and permits
    continuous assignments to drive nets any type of variable.

    TO:

    SystemVerilog removes this restriction, and permits continuous
    assignments to drive nets and variables of any data type.
                              ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

    ----------------------------------------------------------------------
    SECTION 11.5

    CHANGE:

    Any data type can be declared as a class property, except
    for net types since they are incompatible with dynamically
    allocated data.

    TO:

    There are no restrictions on the data type of a class
    property.

    ----------------------------------------------------------------------
    SECTION 19.2:

    CHANGE:

    The aim of interfaces is to encapsulate communication. At the lower
    level, this means bundling variables and wires in interfaces, and can
    impose access restrictions with port directions in modports.

    TO:

    The aim of interfaces is to encapsulate communication. At the lower
    level, this means bundling variables and nets in interfaces, and can
                                             ^^^^
    impose access restrictions with port directions in modports.

    ----------------------------------------------------------------------
    SECTION 23.4:

    CHANGE:

    The $bits function can be used as an elaboration-time constant when
    used on fixed sized types; hence, it can be used in the declaration
    of other types or variables.

    TO:

    The $bits function can be used as an elaboration-time constant when
    used on fixed sized types; hence, it can be used in the declaration
    of other data types, variables or nets.
             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

    ----------------------------------------------------------------------

    SECTION 23.7: Array querying system functions

    CHANGE:

    SystemVerilog provides system functions to return information about a
    particular dimension of an array variable or type.

    TO:

    SystemVerilog provides system functions to return information about a
    particular dimension of an array data object or data type.
                                     ^^^^^^^^^^^^^^^^^^^^^^^^

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