From: Shalom Bresticker (Shalom.Bresticker@freescale.com)
Date: Thu Nov 11 2004 - 05:47:43 PST
I did not find it, either.
Although Verilog-XL produces an error, NC-Verilog only produces a warning, which
and VCS doesn't say anything.
Steven Sharp wrote:
> >There is already a lexical restriction in Verilog for things like a
> >space between two ampersands:
> >A & & B
> BTW, I looked for this restriction in the 1364 LRM to see if there was
> any useful wording, and did not find it. Apparently this is just a
> de fact standard based on the fact that Verilog-XL produces an error
> for it.
> Steven Sharp
-- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478
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