[sv-bc] DataTypes: friendly overview

From: Kathy McKinley (mckinley@cadence.com)
Date: Thu Nov 11 2004 - 16:21:47 PST

  • Next message: Steven Sharp: "Re: [sv-bc] DataTypes: friendly overview"

    Okay, here is a starting point for an overview. Please do not hesitate
    to suggest significant improvements, examples, etc. If you want a rewrite,
    you have to supply it yourself ;-).

    ----------------------------------------------------------------------

    SystemVerilog extended Verilog by adding powerful new data types and
    operators that can be used to declare and manipulate parameters and
    variables. Extensions like packed structs provide a very convenient
    abstraction for manipulating an object that is really just a bit vector.

    SystemVerilog did not extend these new data types to nets. However,
    with the addition of continuous assignments to variables, hardware
    designers can use the extended data types with variables to model
    many common network behaviors. Users would like to have these
    convenient abstractions for nets too, because other common network
    behaviors -- bidirectionality, multiple driver resolution, and delays
    -- cannot be modeled with variables.

    We propose to extend SystemVerilog by making a subset of the new
    data types available for nets too. In this first IEEE revision
    of SystemVerilog, we would like to allow a net or port to have
    any fixed-size data type that is based on four-state logic.
    You can use new SystemVerilog data types to declare parameters and
    variables, and by extension you can use new data types to declare
    nets too. For example:

        typedef struct packed { logic ecc; logic [7:0] data; } MemLoc;
        wire MemLoc memsig;

    This extension for nets is limited to four-state data types because
    of schedule constraints in proposing LRM changes. We would have liked
    to propose two-state extensions as well. It is not our intent to preclude
    the extension of other data types to nets in the future.

    DATA OBJECTS AND DATA TYPES

    You can look at Verilog data objects as having two primary
    characteristics.

    One is the "kind" of the object (i.e., variable vs. parameter
    vs. net) and the other is the "data type" of the object (integer
    vs. real vs. scalar bit, etc).

    Roughly, the object kind indicates what you can do with the object.
    Only parameters can be modified with defparam statements,
    only variables can be assigned by procedural assignments,
    only nets have values that are resolved from their drivers, etc.

    Roughly, the data type of an object indicates the values the object
    can take on. A data object of type 'real' can take on the value 3.14,
    an object of a bit vector type can take on the value 4'b0xz1, etc.

    These two characteristics of a data object are largely orthogonal.
    As examples, a variable can be of any data type, and a bit vector can
    be the data type of any kind of data object.

    Certain kinds of data objects have additional characteristics.
    For example, a net has a "net type", such as wire or trireg, that
    determines how its value is computed.

    The diagram below illustrates these concepts.

      <revised picture sent earlier>

    This diagram shows the relationships between a data object and its
    significant properties. A data object is a construct that has a name
    and a value associated with it. Thus, an important characteristic of
    a data object is the set of values that it can have -- that is, its
    "data type". Certain kinds of data objects have additional properties
    of interest. For example, a variable is also characterized by its
    lifetime, and a net is also characterized by its net type.

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