Re: [sv-bc] DataTypes: wording for optional "var"

From: Steven Sharp (sharp@cadence.com)
Date: Thu Nov 18 2004 - 18:13:47 PST

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    Hey Neil,

    That is quite clever. Treat it as a forward typedef, and if the type is
    eventually found, use that type. If the type is never found, default to
    logic. In that case, it has the same effect as if you had treated it as
    a typedef to the default logic type instead of as a forward typedef. It
    is just the sort of thing that the Verilog language would do too.

    I really hadn't considered anything like that, and I don't think Brad was
    suggesting it either. I think what Brad had in mind was always treating
    this particular syntax as a forward typedef, but allowing the short-hand
    for a typedef of a logic vector. Nobody really needs to create a bunch
    of aliases for a logic scalar type anyway, but they may need a lot of
    different length vector types.

    Steven Sharp
    sharp@cadence.com

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