From: Mark Hartoog (Mark.Hartoog@synopsys.com)
Date: Thu Nov 18 2004 - 19:03:09 PST
I think the most recent versions of the data types on wires proposals look
good to me.
I think the typedef change to omit the type should not be part of the
data types on wires proposal. If people want to pursue this, they can file
a separate item for this.
> -----Original Message-----
> From: firstname.lastname@example.org [mailto:email@example.com]On Behalf Of Kathy
> Sent: Thursday, November 18, 2004 6:25 PM
> To: Greg.Jaxon@synopsys.COM; firstname.lastname@example.org
> Cc: email@example.com; firstname.lastname@example.org
> Subject: Re: [sv-bc] DataTypes: 11/18/04 Meeting Minutes
> Hello Greg,
> Thank you for bringing this improper usage to our attention.
> I have changed "comprised" to "composed".
> >Date: Thu, 18 Nov 2004 13:04:52 -0800
> >From: Greg Jaxon <Greg.Jaxon@synopsys.com>
> >Organization: //Synopsys/ICBU/HDL Compiler
> >To: Kathy McKinley <email@example.com>
> >Cc: firstname.lastname@example.org, email@example.com
> >Subject: Re: [sv-bc] DataTypes: 11/18/04 Meeting Minutes
> >Kathy McKinley wrote:
> >> Replace the paragraph in our proposal that begins
> >> "The effect of this recursive definition is" with the following
> >> two paragraphs:
> >> The effect of this recursive definition is that a net is comprised
> >> entirely of four-state bits, and is treated accordingly. There is no change
> >> to the Verilog-2005 network semantics. In addition to a signal value, each
> >> bit of a net shall have additional strength information. When bits of signals
> >> combine, the strength and value of the resulting signal shall be determined
> >> as in Verilog-2005 section 7.10.
> >Just an english usage note:
> > "is comprised entirely of" should probably say "is composed of".
> > Wholes comprise their parts, and it is incorrect to use "comprise"
> > and then leave out some of the parts - so saying "entirely" is redundant.
> >Greg Jaxon
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