Testbench Example - wire/reg datatypes proposal

From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Tue Dec 14 2004 - 18:57:07 PST

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    Hi, All -

    Attached is a block diagram of a testing scheme I use along with working
    example files. The testing scheme is needlessly complicated because I have
    to declare input-stimulus variables twice, depending on whether the
    testbench is making procedural assignments to the DUT inputs (testbench
    regs) or whether the VECUTIL module is driving sampled values to the DUT
    inputs (testbench wires).

    This is a simple example. For more complex testbench examples, I have to
    declare large numbers of variables to conditionally compile either
    reg-variables or nets. With the wire-reg enhancement, this task becomes
    much easier (only one set of wire declarations would be required).

    To extract the example:
    uudecode wire_reg_example.uu
    uncompress wire_reg_example.tar.Z
    tar xf wire_reg_example.tar

    creates the wire_reg_example directory.

    Change into this directory and try the following:

    <verilog_cmd> -f r1gen.f // generates the stimulus and output pattern
    files and a command option with the appropriate number of vectors. Ignore
    the test-fail message - this is just generating vectors.

    <verilog_cmd> -f r1play.f // causes the VECUTIL module to playback the
    vectors and compare expected patterns to the design output.

    <verilog_cmd> -f r1.f // causes the testbench to generate the vectors
    (not VECUTIL) but still uses VECUTIL to compare actual outputs to expected
    patterns.

    The testbenches get easier if I don't have to declare inputs twice, once as
    regs and once as wires.

    Regards - Cliff

    ----------------------------------------------------
    Cliff Cummings - Sunburst Design, Inc.
    14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
    Phone: 503-641-8446 / FAX: 503-641-8486
    cliffc@sunburst-design.com / www.sunburst-design.com
    Expert Verilog, SystemVerilog, Synthesis and Verification Training



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