Date: Sat May 01 2004 - 11:44:30 PDT
-- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Reuse Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478
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---------- Forwarded message ---------- Date: Sat, 1 May 2004 08:59:34 +0200 From: Vassilios.Gerousis@infineon.com To: email@example.com, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org Subject: [sv-ec] SystemVerilog Technical Planning Meeting on June 3 -- San Jose
Dear SystemVerilog Committee members, SystemVerilog 3.1A standard will require continual efforts on our parts to support Errata based on implementation and usage. We have done this for 3.1 and we will continue doing this for 3.1A. In addition, we will provide interpretation and help for the IEEE committee that will standardize 3.1A. Many of us has spent the last three years developing and enhancing SystemVerilog. We believe this standard is strong and stable to stand on its feet and go through IEEE process based on it completeness. Our plan is to form a working group out of the four ones we have and focus on Errata and interpretation. Part of this activity is to also cooperate with IEEE committee who will standardize SystemVerilog. We will release Errata document on a regular schedule based on EDA implementation feedback and also on usage feedback. The first meeting of this errata committee is planned for June 3rd. It will be in San Jose. It will start at 9:30 AM and spend at least four hours in the organization and definition. We will also define the process of how to work with an IEEE working group that will standardize SystemVerilog. An Agenda and detail will be released soon.
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: Sat May 01 2004 - 11:25:24 PDT
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